JPH0194632A - Method of testing semiconductor integrated circuit device - Google Patents
Method of testing semiconductor integrated circuit deviceInfo
- Publication number
- JPH0194632A JPH0194632A JP62253347A JP25334787A JPH0194632A JP H0194632 A JPH0194632 A JP H0194632A JP 62253347 A JP62253347 A JP 62253347A JP 25334787 A JP25334787 A JP 25334787A JP H0194632 A JPH0194632 A JP H0194632A
- Authority
- JP
- Japan
- Prior art keywords
- external
- external lead
- external leads
- leads
- testing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、例えば、スモールア゛ウドラインパッケー
ジC以下80Fと呼ぶ)工aなどの外部リードの曲りの
検査に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the inspection of bends in external leads of, for example, small outdoor line packages (hereinafter referred to as 80F) and the like.
第4図+ILI〜10;は、それぞれ80P型工Oの平
面図、良品パッケージの側面図、不良品パッケージの側
面図である。Figures 4+ILI to 10 are a plan view of the 80P type machine O, a side view of a non-defective package, and a side view of a defective package, respectively.
図において、+11i工Cのパッケージ本体、I2Nd
パッケージ本体…から導出された外部リードである。In the figure, the package body of +11i engineering C, I2Nd
This is an external lead derived from the package body.
現行のE工AJ(日本電子機械工業会) 、 JKDF
XC!(国際標準規格)タイプの規定による80Fの最
終検査において、外部リード:21の浮き上りの検査は
、目視により行なわれている。Current E-AJ (Japan Electronics Industry Association), JKDF
XC! (International Standard) In the final inspection of 80F according to the type regulations, the inspection for floating of the external lead 21 is performed visually.
従来の目視によるリード121の浮き上りの検査では、
人間の目による検査なので、精度が悪く、不正確で、迅
速な検査を行なうことができず、これらを改善するため
に検査員を増員する必要が生じ、その結果、検査費用が
高価になるという問題があった。In the conventional visual inspection of the lead 121,
Since the test is performed using human eyes, it is inaccurate, has poor accuracy, and cannot be tested quickly. To improve these issues, it is necessary to increase the number of testers, resulting in high test costs. There was a problem.
この発明は、上記のような問題点を解決するためになさ
れたもので、精度が良く、正確で、迅速な検査ができる
とともに、検査費用を低減した工Cの外部リードの曲り
検査を行うことを目的とする。This invention was made in order to solve the above-mentioned problems, and it is an object of the present invention to perform a bending inspection of the external lead of the process C, which enables accurate, accurate and quick inspection, and reduces the inspection cost. With the goal.
この発明に係るICの検査方法は、工0のパッケージ本
体に外部リードの許容変形範囲の変形を生じる荷重を加
え、複数の外部リードの配置に対応して設けられた電極
対に外部リードの端部の平面接触部が接触するか否かを
検査するものである〇
〔作用〕
この発明においては、外部リード端部の平面接触部全電
極対に接触させることにより、外部リードの曲りを検出
することができる。In the IC inspection method according to the present invention, a load that causes deformation of the external leads within the permissible deformation range is applied to the package main body in step 0, and the ends of the external leads are applied to the electrode pairs provided corresponding to the arrangement of the plurality of external leads. Inspection of whether or not the flat contact is contacted or not 〇 [action] In this invention, the external lead bend is detected by contacting the entire electrode of the plane of the external lead end. be able to.
以下1本発明の実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第a図はこの発明の一実施例によるsOPのリード12
1の形状検査方法金示す図、第2図は検査台(61に内
蔵されている検査装置部anの構成を示す回路図、第3
図はICの外部リードの曲りの検出におけるフローチャ
ート図である。図において、…は被検査IOパッケージ
、(21は被検査工Cパッケージfi+の外部リード、
131#f外部リード(2)の先端平面接触部、(41
は先端平面接触部(3が正しい形状全成しているかを検
出する電極対で、被検査IOパッケージIl+の複数の
外部リード(21の配置に対応して設けられる。+61
[被検査工Cパッケージ…の外部リード+21に対して
、それぞれリード曲り許容範囲内であれば外部リード(
21の先端平面接触部(31が、電極対141に接触す
るように設定した荷重、(61は検査装置部uDを内蔵
した検査台、(フ1は電流計、(8)は回路保護低抗、
(10)は定電圧源である。FIG. a shows an sOP lead 12 according to an embodiment of the present invention.
1 is a diagram showing the shape inspection method, FIG. 2 is a circuit diagram showing the configuration of the inspection device part an built in the inspection table (61),
The figure is a flow chart diagram for detecting bending of an external lead of an IC. In the figure, ... is the IO package to be inspected, (21 is the external lead of the C package fi+ to be inspected,
131#f Tip flat contact part of external lead (2), (41
is a pair of electrodes for detecting whether the tip plane contact portion (3) has the correct shape, and is provided corresponding to the arrangement of the plurality of external leads (21) of the IO package Il+ to be inspected.+61
[For the external lead +21 of the C package to be inspected, if each lead is within the allowable lead bending range, the external lead (
(31 is a load set to contact the electrode pair 141, (61 is an inspection table with a built-in inspection device unit uD, (F1 is an ammeter, (8) is a circuit protection low resistance ,
(10) is a constant voltage source.
次に実施例の動作を図を参照しながら説明する。第8図
の6υに示すように、被検査工CIl+の先端平面接触
部(31の位置を複数の電極対141に対しての配置と
複数の外部リードfi+の端部を対応させた状態にし、
検査台(61の上に設置する。Next, the operation of the embodiment will be explained with reference to the drawings. As shown at 6υ in FIG. 8, the position of the tip plane contact portion (31) of the workpiece to be inspected CIl+ is made to correspond to the arrangement with respect to the plurality of electrode pairs 141 and the end of the plurality of external leads fi+,
Installed on the examination table (61).
そして、第8図の(至)に示すように被検査ICパッケ
ージ本体Illの外部リード(21の許容変形範囲の変
形を生ずる荷重15)を被検査IOパッケージ+11全
体に加わるようにする。次に第8図■に示すように、検
査台161の上面に配置した電極対+41と外部リード
telの先端子面接@部(3Iの接触状態を検査する。Then, as shown in (to) in FIG. 8, the external lead (load 15 that causes deformation within the allowable deformation range of 21) of the IC package main body Ill to be tested is applied to the entire IO package +11 to be tested. Next, as shown in FIG. 8 (2), the contact state between the electrode pair +41 placed on the top surface of the inspection table 161 and the tip end surface @ part (3I) of the external lead tel is inspected.
第3図の−に示すように、もし電極対(4)が外部リー
ド(21の先端平面接触部131 Kよって短絡される
と、第8図の鏝に示すように、検査装置部内回路αυに
電流が流れる。その状態を電流計171を通して確認で
きる。(3図のCllIC示すように、先端平面接触部
13)が正しい形状を成していないときは、電極対(4
1は先端平面接触部によって短絡されないので、検査装
置部内の回路ODには電fitifiれず電流計(71
の針は振れない口
以上により、工0の外部リード(21の曲りが電気的に
検出でき、したがって、その良品の判別が容易かつ迅速
にできる。If the electrode pair (4) is short-circuited by the flat tip contact portion 131K of the external lead (21), as shown at − in FIG. Current flows.The state can be confirmed through the ammeter 171.If the tip plane contact portion 13 (as shown in Figure 3) does not have the correct shape, the electrode pair (4
1 is not short-circuited by the tip flat contact part, so the circuit OD in the inspection device section is not electrically fitted and the ammeter (71
Since the needle does not swing, bends in the external lead (21) can be detected electrically, and therefore, it is possible to easily and quickly determine whether the product is a good product or not.
上記実施例では検査装置sun内の回路に定電圧源t1
01を用いたが、定電圧源(10)のかわりに定電流源
を用いて回路を構成しても、上記実施列と陶様の方法に
より同様の効果を得ることができる。また、上記実施例
では、80Fの場合について説明したが、電極対+41
の配置やその数を変えることで、80P以外の表面実装
型のICパッケージの外部リードについても同様の検査
効果を奏する。In the above embodiment, the constant voltage source t1 is connected to the circuit in the inspection device sun.
01 was used, but even if the circuit is constructed using a constant current source instead of the constant voltage source (10), the same effect can be obtained by the above-mentioned embodiment and the method of Sue. Further, in the above embodiment, the case of 80F was explained, but the electrode pair +41
By changing the arrangement and number of the 80P, a similar inspection effect can be obtained for the external leads of surface mount type IC packages other than 80P.
以上のように、この発明によればICのパッケージ本体
と外部リードの許容変形範囲の変形を生じる荷重會卯え
複数の外部リードの配置に対応して設けられた電極対に
外部リードの端部の先端平面接触部が接触するか否かを
検出−するようにしたので、正確かつ安価にICの外部
リードの検査ができる効果を有する。As described above, according to the present invention, the ends of the external leads are fixed to the electrode pairs provided corresponding to the arrangement of the plurality of external leads in a load combination that causes deformation within the permissible deformation range of the IC package body and the external leads. Since it is detected whether or not the flat end contact portion of the IC makes contact, it is possible to accurately and inexpensively inspect the external leads of the IC.
第1図はこの発明の一実施例による工0の外部リードの
曲り検査装置を示す説明図、第2図は第1図の検査装置
の検査製置部回路図、第3図は第1図の動作金示すフロ
ーチャート図、第4図1al 、 ftn 、 +ol
それぞれHeop工oの平面図、良品so’pICの外
部リード(2)の先端平面接触部131の形状全表した
図、および不良品パック−ジの外部リード+21の先端
平面接触部13ンの変形の状態を表わした図である。
図において、…は半導体集積回路装置パッケージ本体、
(21は外部リード、131は先端子面接軸部、+41
は電極対、16+は荷重、16)は検査台、(7)は電
流計、(81は回路保護低抗、(9)はスイッチ、fl
olは定電圧源、aでは検査装置部である。
なお、図中同一符号は同−又//′i相当部分を示す。FIG. 1 is an explanatory diagram showing an apparatus for inspecting bending of external leads with 0 steps according to an embodiment of the present invention, FIG. 2 is a circuit diagram of the inspection and manufacturing section of the inspection apparatus shown in FIG. 1, and FIG. Flowchart showing the operation of Figure 4, 1al, ftn, +ol
A plan view of the Heop IC, a diagram showing the entire shape of the tip flat contact part 131 of the external lead (2) of the good product so'pIC, and a deformation of the tip flat contact part 13 of the external lead +21 of the defective package. FIG. In the figure, ... is the semiconductor integrated circuit device package body,
(21 is the external lead, 131 is the tip surface shaft, +41
is an electrode pair, 16+ is a load, 16) is an inspection table, (7) is an ammeter, (81 is a circuit protection resistor, (9) is a switch, fl
ol is a constant voltage source, and a is an inspection device section. In addition, the same reference numerals in the drawings indicate the parts corresponding to the same - or //'i.
Claims (1)
リードの曲りを検出する検査において、前記外部リード
の許容変形範囲の変形を生ずる荷重を前記ICのパッケ
ージ本体に加え、前記外部リードの配置に対応して設け
られた電極対に前記外部リードの先端の平面接触部が接
触しているか否かを電気的に検査することにより、前記
外部リードの曲りを検出することを特徴とする半導体集
積回路装置の検査方法。In an inspection to detect bending of a plurality of external leads of a semiconductor integrated circuit device (hereinafter referred to as an IC), a load that causes deformation of the external leads within an allowable deformation range is applied to the package body of the IC, and the arrangement of the external leads is changed. A semiconductor integrated circuit characterized in that bending of the external lead is detected by electrically inspecting whether or not a planar contact portion at the tip of the external lead is in contact with a correspondingly provided electrode pair. How to test equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62253347A JPH0194632A (en) | 1987-10-06 | 1987-10-06 | Method of testing semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62253347A JPH0194632A (en) | 1987-10-06 | 1987-10-06 | Method of testing semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0194632A true JPH0194632A (en) | 1989-04-13 |
Family
ID=17250064
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62253347A Pending JPH0194632A (en) | 1987-10-06 | 1987-10-06 | Method of testing semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0194632A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5270830A (en) * | 1989-08-10 | 1993-12-14 | Fujitsu Limited | Facsimile transmission system |
-
1987
- 1987-10-06 JP JP62253347A patent/JPH0194632A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5270830A (en) * | 1989-08-10 | 1993-12-14 | Fujitsu Limited | Facsimile transmission system |
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