JPH0195332A - Logical type information processor - Google Patents

Abstract

PURPOSE:To attain high speed execution without an unnecessary memory access by aborting the memory access with comparison between a tag value to designate the memory access by a pointer with a tag and the tag in the pointer with the tag. CONSTITUTION:A memory access control part 8 compares the tag which accompanies an address to be supplied to an MAR3 with the tag value to be supplied from a pipe line register 7 as an immediate value. Then, whether the memory cycle is apported or not is determined. As preparation for a case that the contents of get-list-Ai are an REF, an instruction is issued to the control part 8 so that memory activation can be loaded and the memory cycle can be aborted simultaneously when the tag of the Ai is not the REF. A multi- way jump is executed to the tag processing routine of LIST, UV, REF and others by the tag value of the Ai. Thus, the unnecessary memory access does not occurred and an over-head is not generated.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a knowledge information processing device suitable for executing a predicate logic language such as Prolog, and in particular to a knowledge information processing device suitable for executing a predicate logic language such as Prolog. The present invention relates to a logical information processing device having an access method.

(Prior art) Conventional procedural language @ (Fortran, C, Cobo
In a logical language such as Prolog, the processing content changes depending on the type of data.

Therefore, in order to efficiently execute such a logical language at high speed, a tag indicating the type of data is added to all data. An example of this tagged data is shown in FIG.

In this way, since all data is represented as tagged data,
Since the hardware can change the processing content of the data section by evaluating the tag section, high-speed execution is possible.

Let us now consider the operation of the hardware in more detail. D.
Considering the execution of the instruction get-1ist Ai in the H, DWavven Proloy instruction set, the processing is as shown in FIG. 6, depending on the tag value of the Ai register.

At 5tep l, multiway jump is performed according to the tag value of Ai, and if the tag value is 'REF', A
Since the contents of i are seven pointers, new data is read from the AiK memory using the data section of Ai as an address. If the tag value is ILIST+, '
If it is UV', LIST processing and variable processing are performed, and if the Tag value is other data, backtracking occurs due to fail processing.

The problem here is when the tag value is 'REFI', and after checking the tag value, memory access is started, which requires a large number of processing steps and slows down the process.

In order to prevent this processing speed from decreasing, in case the tag value is IREF' at 5 tep 1, memory is started at the same time as the multi-way jump based on the tag value at 5 tep 1. The access is valid only when Tag = 'REF'; in other cases, it is a meaningless memory access. If the cache memory was not hit due to this meaningless memory activation, the cache memory would load meaningless data from the main memory, causing a large overhead.

(Problems to be Solved by the Invention) As described above, according to the conventional method, memory activation was performed at the same time as the multiway jump based on the tag value, which resulted in frequent unnecessary memory accesses, which resulted in a large overhead. There was.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a logical information processing device that performs high-speed execution without unnecessary memory access.

[Structure of the invention]

(Ninth Means for Solving the Problems) The present invention provides a logical information processing device that processes tagged data, in which the value of a tag that specifies memory access by a tagged pointer and the tag in the tagged pointer are It is characterized by having means for shearporting by comparison.

(Operation) The present invention specifies a memory address represented by a tagged pointer and a tag as an access attribute at the time of memory activation, and compares the two tags to determine whether or not to abort memory activation. It is characterized by having the means.

(absolutely defeated) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention.

1 is the register file, 32 bits 64 words
.

Has capacity. It is possible to write from two boats and read from two boats at the same time.

2 is an ALU that performs calculations on two 32-bit data read from the register file. The output of ALU2 can be written to MAR3 through register file 1 and data selector 5EL9. 4 is a cache memory, which outputs the data corresponding to the address given by MAR, 3 and MR, D51C, and writes it into the register file 1. 6 is a ROM that stores a microprogram for overall control. The control information is latched in the pipeline register 7 and then supplied to each section. 8 is a part that controls memory access, and compares the tag attached to the address supplied to MAR with the tag value supplied as an immediate value from the pipeline register, and determines whether or not to abort the memory cycle. decide. Under what conditions the two tag values should abort a memory cycle is directly instructed from the pipeline register 7 as aport control information.

FIG. 2 shows a detailed diagram of the inside of the memory access control section. The memory access control section is specified by the pipeline register. The operation shown in FIG. 3 is performed according to the port control information.

The above g when having a memory access control section
The et-1ist Ai processing flow is as shown in FIG. This processing step is controlled by a microprogram stored in the OM6.

At 8tepl, in preparation for the case where the content of Ai is l REF l, the memory is activated, and at the same time, if the tag of Ai is not l REF l, an instruction is given to the memory access control unit to abort the memory cycle. . Also, in the same step, depending on the tag value of Ai,
1LI8Tl 'UVI'REFI Performs a multi-way jump to other tag processing routines. By doing this, unless memory data reading is really necessary (Tag='REF'), memory cycles are aborted, so no unnecessary memory access is caused and no overhead is generated.

In this example, the memory activation and appoint conditions are instructed in the same microstep, but if the memory cycle takes multiple cycles, the tag determination is performed in a subsequent step after the memory activation and the memory activation is performed. It is also possible to stop recycling midway.

It is also possible to add a function to appoint if the cache is not hit, a function to appoint if a main memory page fault occurs, and a function to appoint if a transaction violation occurs to the appoint specification conditions.

In this case, it is necessary to make the appointment information referenceable as the status information.

゛Also, it is necessary to traverse the memory until data that is not I REF ' is read from memory, but the memory control section does not have l RB.
By providing a Fl data check function and traversing the memory independently of microprogram control, it is possible to speed up the traversal processing.

〔Effect of the invention〕

According to the present invention, memory access is performed simultaneously with a multiway jump based on a tag value when Tag =
Limited only to 'REF'. Therefore, high-speed execution is possible without unnecessary memory access, and its practical advantages are enormous.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of an embodiment of the present invention, FIG. 2 is a block diagram of memory control in an embodiment of the present invention, and FIG.
FIG. 4 is a diagram showing the function of memory control according to an embodiment of the present invention, FIG. 4 is a processing flow diagram of tagged data according to an embodiment of the present invention, and FIG. FIG. 6, which is a diagram showing the data structure, is a processing flow diagram of tagged data according to the conventional method. 1...Register file, 2...ALU, 3...
MAR14...cache memory, 5...MRD,
5... Micro program memory, 7... Pipeline register, 8... Memory access control,
9...SEL. Agent Patent Attorney Nori Ken Chika Yudo Hikaru Matsuyama 2 Figure 2 Figure 3 Figure 5

Claims (1)

[Claims] A logical information processing device that processes tagged data, characterized by comprising means for aborting memory access by comparing a tag value specifying memory access by a tagged pointer with a tag value in the tagged pointer. A logical information processing device.