JPH0195555A - Manufacture of bipolar semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention enables device isolation with a shallow isolation layer and achieves high BVc without forming a deep collector layer.
The present invention relates to a method of manufacturing a bipolar semiconductor integrated circuit device that can simultaneously achieve Eo (base voltage when collector-emitter is open) and low collector resistance.

(Prior Art) The use of antimony oxide as a diffusion source and nitrogen gas containing a small amount of oxygen as a diffusion source in a method of manufacturing a semiconductor integrated circuit device is disclosed in Japanese Patent Application Laid-open No. 121634/1983. , a technique in which a glass film containing impurities is provided on a desired diffusion layer region on the surface of a semiconductor substrate, and a protective film containing no impurities is provided only on the surface of the semiconductor substrate that is not covered with this glass film to perform diffusion is disclosed in JP-A-58. -322
It is disclosed in Publication No. 5.

Furthermore, regarding metal corrosion inhibitors containing compositions containing zinc chromate and sulfamic acid,
This is disclosed in Japanese Patent No. 68.

Also, the first regulating body determines the flow rate of gas passing through the valve by moving the movable valve element, and the second regulating body provides a flow rate greater than or equal to the determined flow rate.

It is shown in Japanese Patent Publication No. 50-30294.

FIG. 2 is a sectional view of an NPN transistor region of a semiconductor integrated circuit device constructed by a conventional manufacturing method. In this FIG. 2, 21 is a P-type semiconductor substrate %22 and
23 is an N-type buried layer formed on the M semiconductor substrate 21; 23 is an N-type epitaxial layer grown on the P-type semiconductor substrate 21;
4 is P type isolation.

Nu! Base layer 26 of epitaxial layer 23KPffi
is formed, and an N-type emitter layer 27 is formed on this P-type base layer 26.

Further, a deep collector layer 25 is formed in the N-type epitaxial layer 23, and a collector contact layer 27a is formed on this deep collector layer 25 at the same time as the emitter layer 27.

Furthermore, the insulating film 29 formed on the entire upper surface is patterned to form an emitter electrode 28 on the emitter layer 27, a base electrode 28a on the space layer 26, and a collector electrode 28 on the collector contact layer 27a. By the way, the svcg of the NPN) transistor shown in FIG.
o largely depends on the thickness of the epitaxial layer 23. For example, in order to secure BVCEO50V when the hFE (common emitter direct current amplification factor) of an NPN transistor is about 80, the resistivity is 5Ω, the secondary epitaxial layer 23 is formed, and the distance between the buried layer 22 and the base layer 26 is 6 μm or more. It has been experimentally confirmed that it must be set so that

This is because the depletion layer formed at the base junction is
This is because the key to determining the B VCKO of an NPN transistor is whether it can sufficiently spread to the collector side without being suppressed by the pressure.

However, increasing the thickness of the epitaxial layer 22 in order to increase avcr:ot- also increases the distance between the buried layer 22 and the collector contact layer 27a, and as a result, the collector resistance of the NPN) run source also increases. The problem was that it got too big.

That is, increasing the aVcxot of an NPN transistor and decreasing the collector resistance are contradictory to each other, and conventionally, one has been achieved at the expense of the other.

(Problem that the invention attempts to solve) The traditional way to solve this problem is.

Form a sufficiently thick epitaxial layer and replace it with N
There is a method of forming a type DIG collector layer 25, but in this method, both the isolation layer 24 and the DIG collector layer 25 must be deeply diffused.
This also means that the lateral diffusion also increases, which ultimately leads to a reduction in device alignment.

This invention solves the problems of the above-mentioned prior art.
A bipolar semiconductor integrated circuit that solves the problems of requiring deep diffusion in both the isolation layer and deep collector layer, the inability to increase BVCEO, the inability to obtain low collector resistance, and the impediment to device miniaturization. A method for manufacturing the device is provided.

(Means for Solving the Problems) The present invention provides a method for manufacturing a bipolar semiconductor integrated circuit device in which a semiconductor substrate of a first conductivity type is etched into an arbitrary/main turn, and a part of the etched region is etched. a step of forming an impurity layer of a second conductivity type opposite to the first conductivity type in a region including the first conductivity type, and depositing an epitaxial layer of a second conductivity type in the etched region of the semiconductor substrate, and a step of depositing an epitaxial layer of a second conductivity type in a region other than an arbitrary pattern. In this method, a step of forming an isolation layer is introduced.

(Function) According to the present invention, the above steps are introduced in the method for manufacturing a bipolar semiconductor integrated circuit device.
The second conductivity type impurity layer serves as a buried layer 9, and this buried layer is connected to the collector contact layer of the epitaxial layer to obtain a sufficiently low collector resistance. Well spaced and high BVCI
Therefore, the above-mentioned problem can be eliminated.

(Example) Hereinafter, an example of the method for manufacturing a piezo-type semiconductor integrated circuit device of the present invention will be described with reference to the drawings. FIG. 1(4) to FIG. 10 are process sectional views of one embodiment. First, as shown in FIG. 1(4), a P-type semiconductor substrate l
The planned pace area is etched by an ion reactive etching method using a fluorine-based gas using Resost 2, which has undergone a known photolithography process, as a mask. The reason why the ion reactive etching method is used at this time is to make it easier to planarize the surface of the element using selective epitaxial etching later.

Next, as shown in FIG. 1(B), a coating containing an impurity that will become a diffusion source is applied on the oxide film 3t as a diffusion mask to a region including a part of the etched region, and an oxide film for the diffusion source is formed. 4 is formed and an N-type impurity (eg, antimony) is diffused to form a diffusion layer 5.

Next, as shown in FIG. 1C, the grooves formed in the semiconductor substrate 1 by the etching are filled and planarized using a single selective epitaxial method. This selective epitaxial
It may be carried out using known equipment and under conditions suitable for each equipment, but in general, in order to improve monoselectivity and crystallinity, it is preferable to perform deposition at a relatively low temperature of about 900°C and under reduced pressure of about 20 torr. be.

The source gas at this time is preferably Si-α, but
In order to reduce the facet F formed around the epitaxial region, an appropriate amount of HC1 is applied at the same time! It is desirable to flow gas.

In FIG. 1(C), 6 is an oxide film in which the epitaxial region is apertured, and 7 is an N-type epitaxial layer selectively deposited.

Subsequently, as shown in FIG. 10, after removing the oxide film 6 on the surface with a hydrofluoric acid-based solution, an N-type epitaxial layer 7a is formed.
is deposited on the entire surface of the substrate. At this time, either reduced pressure or normal pressure may be used.

Next, as shown in FIG. 1, an isolation layer 8 is formed in the area other than the etched area.

Therefore, the junction depth can be shallow, and the heat treatment for diffusion can be performed at a relatively low temperature and in a short time, so that the lateral spread of the impurity layer is small, making it ideal for scaling down devices.

After this, similarly to the prior art, after forming the P-type space layer 9 on the N-type epitaxial layer 7a, N
Emitter layer lO and collector contact layer 10a of the mold
is simultaneously formed, and the insulating film 12 formed on the entire upper surface is turned to form an emitter layer lO through the contact hole.
an emitter electrode 11. electrically connected to the emitter electrode 11. A base electrode 11a electrically connected to the space layer 9 and a collector electrode 11b electrically connected to the collector contact layer 10a are formed.

It should be noted that if the thickness of the 9% N-type Evitator layer 7a shown in FIG. ,
This is convenient for reducing collector resistance.

In addition, in the description of the above embodiments, NPN (Lancester) was taken up as an example, but the conductivity type is N type and P type is the same even if it is opposite to the above, and the polarity is not limited.

(Effect of the invention) As described in detail above, according to the present invention.

In the transistor, since the buried N-type layer and the collector contact layer are connected, a sufficiently low collector resistance can be obtained.

Furthermore, at the same time, a sufficient distance is maintained between the buried layer and the paste layer, making it possible to achieve a high BVcr;o.

Therefore, with the present invention, it is possible to realize a transistor that simultaneously satisfies "reducing collector resistance" and improving rBVcEo, which are contradictory to conventional technologies, and is an essential and useful transistor for realizing high-speed, high-voltage elements. It's technology.

[Brief explanation of the drawing]

1(4) to 1■ are process cross-sectional views of an embodiment of the method for manufacturing a bipolar semiconductor integrated circuit device of the present invention, and FIG. 2 is a cross-sectional view of an NPN transistor region of a conventional semiconductor integrated circuit device. It is a diagram. l...P-type substrate, 2...resist), 3.6...oxide film. 4... Oxide film for diffusion source, 5... Buried layer, 7...
-Epitaxial layer, 7a...N-type epitaxial layer, 8...Isolation layer, 9...Pace layer, 1
0...Emitter layer, 10m...Collector contact layer, 11...Emitter electrode% lla...Pace electrode, llb...Collector electrode. Figure 1

Claims (1)

Scope of Claims: (a) a step of etching a semiconductor substrate of a first conductivity type in an arbitrary pattern; (b) a step of etching a semiconductor substrate of a first conductivity type in a region including a part of the etched region; (c) forming a buried layer by filling the etched region with an epitaxial layer of a second conductivity type; (d) forming a second impurity layer on the surface of the semiconductor substrate; A method for manufacturing a bipolar semiconductor integrated circuit device, comprising: depositing a conductive epitaxial layer; and (e) forming an isolation layer in a region other than the arbitrary pattern on the semiconductor substrate.