JPH0196565A - Method and circuit for synchronization - Google Patents

Abstract

PURPOSE:To prevent the generation of a jitter by preventing a gate signal from being generated by a trigger pulse, when the trigger pulse has been applied in a period in which there is the possibility that the jitter is generated immediately after a first hold-off signal has been ended. CONSTITUTION:To clock input terminals CK1-CK4 of FFs 11-14, OR gates 21-24 are connected. To one input of the OR gates 21-24, a trigger signal from an input terminal 30 is applied through an OR gate 27. An output Q1 of the FF 11 outputs a gate signal, it is applied to a saw tooth wave generator 18, a saw tooth wave is generated, and when it has reached a level of a prescribed comparing signal, a second hold-off signal HO2 and a first hold-off signal HO1 are generated for a prescribed period. In case a trigger pulse has been applied after the signal HO1 has been ended, and before the signal HO2 is ended, a waiting state is made, a gate signal is generated by the next pulse, and during the generating period of this gate signal, even if the trigger signal is applied, it is inhibited to apply the trigger pulse.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an oscilloscope synchronization method and its circuit.

Oscilloscopes need to stably observe various waveforms ranging from low frequencies to high frequencies. For this purpose, a signal that is synchronized with the repetition of the signal under test is required.
Therefore, if the repetition frequency of the observed signal is low, a signal synchronized with each signal is obtained, and if it is high, a signal with a constant repetition frequency or less synchronized with every few repeated signals is obtained. must be obtained without jitter. Specifically, the present invention relates to an improvement in such a synchronization method and circuit, and in particular to a synchronization method and circuit for a cathode ray tube oscilloscope or a sampling oscilloscope suitable for observing high frequency signals.

[Prior Art] The circuit configuration of a synchronous circuit used in a conventional cathode ray tube oscilloscope or sampling oscilloscope will be explained with reference to FIG. 7, and a time chart showing waveforms of each part thereof with reference to FIG.

In FIG. 7, 15 and 16 are both D flip-flops, 25 and 26 are OR gates, and a gate signal synchronized with the trigger signal applied to the input terminal 30 is obtained at the output terminal Q5 of the D flip-flop 15. This is applied to the sawtooth wave generator 19 to generate and output a sawtooth wave. In a cathode ray tube oscilloscope, this is used as a sweep signal for the time axis, and in a sampling oscilloscope, this is compared with a comparison signal that changes extremely slowly, such as a staircase wave or a slow sawtooth wave, and is used as a high-speed sawtooth wave to obtain a strobe pulse. There is.

In FIG. 8, (a) shows the trigger pulse P applied to the input terminal 3o. (b) shows a sawtooth wave generated and output by the sawtooth wave generator 19. (C) shows the output waveform of the output Q5 of the D flip-flop 15. In (d), after the sawtooth wave generator 19 generates a sawtooth wave, a bold off signal HO is outputted to prevent the generator from receiving the gate signal until it has sufficiently recovered.
It is shown. Here, the hold-off signal HO is (
In d), the “Hn level” is shown, and this H′′
The period of is determined by circuit constants. (e) shows the output of the D flip-flop 16.

6 is shown.

A trigger pulse P shown in (a) is applied to the input terminal 30. When the up edge of is applied, Q5 shown in (C) becomes H'', and the sawtooth wave generator 19 generates the sawtooth wave shown in (b). When the sawtooth wave reaches the level of a predetermined comparison signal, (The bold-off signal HO shown in d> is output as “H10,” and the output Q6 of the D flip-flop 16 is
T1 and the output (gate signal) 05 of the D flip-flop 15 shown in (C) as "L II", thereby (
Finish the sawtooth wave shown in b). After a certain period of time (hold-off period) has elapsed, the hold-off signal shown in (d) ends and becomes "'L", making it possible to respond to the trigger pulse P1 applied thereafter. In such a state, when the up edge of trigger pulse P1 is applied to clock terminal CK6 via OR gate 26, D
The flip 70 knob 16 immediately responds because the hold-off signal applied to its reset terminal R6 is always "Ltt" and the D terminal D6 is always connected to the "HIf level". Q6 shown in (e) is "'H
It becomes Pa.

D@child D5 of the D flip-flop 15 is “H”,
Since the hold-off signal HO applied to the reset terminal R5 is "L", the trigger pulse P shown in (a)
When the up edge of 2 is applied to the clock terminal CK5 through the OR gate 25, the D flip 70 block 15
In immediate response, Q5 becomes ta Hve and (b)
The sawtooth wave shown in (d) is generated, and when the level of the predetermined comparison signal is reached, the hold-off signal HO shown in (d) is
In order to reset both D flip-flops 15 and 16 by applying this to the reset terminals R5 and R6, the respective outputs Q5.1l=j and Q6 are set to "L".
Make it tt. This operation is repeated.

In the above operation, when the sawtooth wave reaches the predetermined comparison signal shown in FIG. 8(b), the hold-off signal HO shown in FIG.
os and terminates the sawtooth wave shown in (b). Therefore, for convenience of explanation, the diagram shows that after the comparison signal of (b>) and the sawtooth wave intersect, some time passes until the peak voltage is reached, but in reality, the comparison signal and the sawtooth wave intersect. There is almost no time elapsed until the peak voltage is reached, and the level of the comparison signal and the peak voltage of the sawtooth wave almost always match.

During the above operation, in Fig. 8 (a), the trigger
Even if another trigger φ pulse is applied between pulses Po and Pl, the hold-off signal HO shown in (d)
Since the reset terminals R5 and R6 of the flip-flops 15 and 16 are reset, the output Q5, which is the gate signal, will not be interrupted by another trigger pulse.

Depending on the trigger pulse P1 applied thereafter, the gate signal is not immediately output, and the output Q6 is set to °°H' to wait for the application of the next trigger pulse P2. The output Q5, which is the gate signal outputted by the trigger pulse P2 applied in this state, does not generate jitter. Therefore, this circuit is extremely useful when the repetition frequency of the trigger pulse P is high.

However, the repetition frequency of the trigger pulse P is
For example, if it is extremely low such as 100H2,
In order to obtain output Q5, which is one gate signal, by trigger pulse P2, trigger pulse P
1, it is necessary for the output Q6 to be set to "H'", and the repetition frequency of the output Q5, which is a gate signal for this purpose, decreases to 50H2, which is one-half of 100H7. In this case, the repetition frequency of the sawtooth wave output from the sawtooth wave generator 19 is also 50H7,
In the case of a cathode ray tube oscilloscope, the screen is drawn 50 times per second, making the screen brightness insufficient. This was extremely inconvenient when observing low signals. Also, with a sampling oscilloscope, if the sampling points that make up one screen are set to 1000,
It takes 20 seconds to compose one screen, which is extremely inconvenient when observing signals with extremely low repetition frequencies, as is the case with cathode ray tube oscilloscopes.

Therefore, when observing a signal with such a low repetition frequency, the repetition frequency of the gate signal should be
A circuit is used that is equal to the repetition frequency of the pulse. This circuit configuration is shown in FIG. 9, and a time chart showing waveforms at each part thereof is shown in FIG. 10, and will be explained. Here, parts corresponding to those shown in FIG. 7 are given the same numbers or symbols.

The difference between the circuit shown in Fig. 9 and the one shown in Fig. 7 is as follows:
Retriggerable one-shot multivibrator 17
is added, and the trigger pulse P applied to the input terminal 30 is applied to the up edge operation input terminal A7, (a)
Trigger pulse P shown in . The output knot Q7 of (f), which had become “Let” due to the application of
, and the output knot Q7 is applied to the set terminal S6 of the D flip 70 knob. Therefore, D
The operation of flip-flops 15 and 16 is controlled by the set terminal S.
The circuit is the same as shown in FIG. 7 except when 6 becomes "H".

9 and 10, the input terminal 30 (a)
When the up edge of the trigger pulse Po shown in FIG. Output Q6 is “HI”
T, the D flip-flop 15 immediately becomes “H”.
'', the sawtooth wave shown in (b) is output, and the output knot Q7 becomes L''. When the sawtooth wave reaches the level of the comparison signal (d>), the hold-off signal HO shown in
', resets the D flip-flop 16, sets its output Q6 to "L", sets the output Q5 of the D flip-flop 15 shown in (C) to "L If", and thereby the saw shown in (b) When a certain period of time (hold-off period) has elapsed, the hold-off signal shown in (d) becomes "L In". Now, if the output pulse width of the retriggerable one-shot multivibrator 17 is set to, for example, 100 μs, then when 100 μs elapses after the output knot Q7 becomes “L II” and no pulse P is applied. ,(f)
As shown in FIG. .In a transient state where this input terminal D5 becomes "H99", (a)
When the up edge of the trigger pulse P1 shown in FIG. Sawtooth waves also produce jitter, as shown by diagonal lines. When this sawtooth wave reaches the level of a predetermined comparison signal, the hold-off signal HO shown in (d) is changed to Hu as shown in (d), but this also causes jitter as shown by the diagonal line.

Since the jittered sawtooth wave is used to sweep the cathode ray tube surface, it also causes jitter in the waveform on the cathode ray tube oscilloscope tube surface.In the case of a sampling oscilloscope, jitter also occurs in the strobe pulse, which also causes jitter on the tube surface. This causes jitter in the waveform.

When the hold-off signal HO shown in (d) becomes “H”,
Since the reset terminals R5 and R6 are set to "Hu", the D flip-flops 15 and 16 are reset, and their output Q
5 and Q6 also become "L" with jitter indicated by diagonal lines, as shown in (C) and (e). Output Q5 is “L”
11, the sawtooth wave shown in (b) also ends with jitter.

Retriggerable one-shot multivibrator 17
The output knot Q7 of becomes “y” again when the up edge of trigger pulse P1 is applied, and then becomes 100
After μs elapses, it becomes “Hee”, so in the transient state where the output Q6 becomes “H”, the trigger pulse P
When an up edge of 2 is applied, as mentioned above, the output Q
5 causes jitter, and the sawtooth wave shown in (b) also causes jitter.

Trigger pulses P1 and P2 cause this output Q6 to
If the output Q5 is applied after a transient state of
Therefore, a jitter-free sawtooth wave or strobe pulse can be generated.

[Problems to be Solved by the Invention] According to the conventional circuit shown in FIG. 9, the repetition period of the trigger pulse P is a retriggerable one-shot φ.
If the pulse width is shorter than the set pulse width of the multivibrator, the output Q6 is generated by the trigger pulse P1 that precedes the trigger pulse P2 that generates the sawtooth wave as shown in Figure 8.
When the trigger pulse P2 is applied, the gate output Q5 is set to HIt and the sawtooth wave is generated (firing) as the standby state (arming state). In order to fire with trigger pulse P2, we were able to obtain a jitter-free gate output Q5 and a sawtooth wave.

Further, when the repetition period of the trigger pulse P is greater than a certain value, for example, 100 μs, the set terminal S6 is set by the not output Q7 of the retriggerable one-shot multivibrator 17, and the output Q6 is set to “HII”. Each time a trigger pulse P is applied,
The same number of jitter-free gate outputs Q5 was obtained, and a sawtooth wave was obtained.

However, as explained using FIG. 10, for example, 100 μs has passed since the previous trigger pulse Po, and no trigger pulse P is input during that time, and the output knot Q of the retriggerable one-shot multivibrator
7 becomes "H" and the output Q6 is set to "H99" in a transient state where the standby state is about to occur, the trigger pulse P1
(or P2), the gate output Q5 causes jitter, and there is a problem that jitter also occurs in the sawtooth wave.

[Means for Solving the Problems] The present invention has been made in order to solve these problems. For this purpose, first and second holdoff signals are obtained from a sawtooth wave generator, and the first and second holdoff signals are held for a certain period of time when the sawtooth wave reaches the level of a predetermined comparison signal. Off (“H”
), and the second holdoff signal returns to "L pt" a little later than the first holdoff signal, and the present synchronous circuit operates using these first and second holdoff signals.

It includes a gate that receives a trigger signal and outputs the trigger signal as a trigger pulse only during a period in which there is no gate signal, and a first and second D flip 70, and responds to a trigger pulse of a predetermined repetition frequency. The first hold-off signal is applied to the reset terminals of the first and second D flips 70 to operate in the same manner as the conventional circuit, and the gate signal is applied during the period when the first hold-off signal is "T1". The second D flip 70 is activated by the pulse one before the trigger number pulse that should not be output and should obtain a gate signal.
The output of the knob is set to “H”, and the next applied trigger
A gate signal is generated by a pulse.

Furthermore, third and fourth D flip-flops are provided, a second hold-off signal is applied to the D terminal of the third D flip-flop, a trigger pulse is applied to the clock input terminal of the fourth D flip-flop, and the 4D flip 7
"Hu" is applied to the D terminal of the 0th block, a gate signal is applied to its reset terminal, and the output of the 4th D flip-flop and the trigger pulse are applied to the clock input terminal of the 3rd D flip-flop via an OR gate. so that it applies
The knot output of the 3rd D flip-flop 70 was connected to the set terminal of the 2nd D flip-flop.

[Operation] The first hold-off signal that may cause jitter is “
At the point when it changes from Htt to
When the pulse is applied, if the knot output of the third D flip-flop is "H", the knot output is set to "L".
As for It, the application of a trigger pulse causes the device to enter the standby state, and the subsequent trigger pulse causes the device to fire.

Therefore, when a trigger pulse is applied in a state where jitter may occur, that is, when the first holdoff signal changes from "H99" to "LIT" and the second holdoff signal remains "HIf",
Since the standby state is created by the trigger pulse that precedes the trigger pulse that causes firing, no jitter occurs in firing.

Furthermore, when a trigger pulse is applied during a transition state to a standby state, jitter may occur once, but no jitter will occur from then on.

Furthermore, since no trigger pulse is applied during the period when the gate signal is present, there is no unstable operation and no jitter.

[Example] An example of the circuit configuration when the present invention is used in a cathode ray tube oscilloscope or a sampling oscilloscope is shown in Fig. 1, and time charts that are waveform diagrams of each part are shown in Figs. 2 to 6. explain.

Here, corresponding elements in FIGS. 7 to 10 are shown using the same symbols.

In FIG. 1, 11 to 14 are D flip-flops,
Each clock input terminal CK has an OR gate 21 to
24 are connected. These OR gates 21-24
One input of the input terminal 30 is connected via an OR gate 27.
A full trigger signal is being applied. The output Q1 of the D flip-flop 11 outputs a gate signal, which is applied to the sawtooth wave generator 18 to generate a sawtooth wave, and when the level of the predetermined comparison signal is reached, the second holdoff signal HO2 and the first holdoff signal are output. The off signal HO1 is generated for a certain period of time (to "H99").

The completion of the second hold-off signal 1-f02 is longer than the time required for the first hold-off signal HO1 to end and its "L It level to settle down sufficiently (for example, 10 nm).
S), the period of the fastest sawtooth wave (e.g. 100n
The timing is set to be delayed by a shorter time than S>. The reason why the end of the second hold-off signal HO2 is slightly delayed than the end of the first hold-off signal HO1 is that the D flip-flop 11, which is reset by the first hold-off signal HO1, causes jitter. This is limited to the time when the hold-off signal HO1 changes from 'H' to 'L' at the end of the hold-off signal HO1 and immediately after that, so in order to remove jitter at this time, the first hold-off signal H is
If the termination of the second hold-off signal HO2 is delayed than the termination of O1, and the trigger pulse P is applied to the input terminal 30 during this time, the set terminal S2 of the D flip-flop 12
One of the trigger pulses that should be fired with
The standby state is created by the previous pulse.

Here, if the up edge of the trigger pulse is applied while the sawtooth wave is being generated, the D flip-flop 13 will operate, so in order to prevent this, an OR gate is gated with the gate signal for sawtooth wave generation. 27 are provided.

The operation of the circuit shown in FIG. 1 will be explained below using the time charts shown in FIGS. 2 to 6. In these time charts, (a) shows the trigger signal applied to the input terminal 30, and (b) shows the trigger pulse P gated by the OR gate 27 and multiplied by 1q. (C) shows the output Q2 of the D flip-flop, and (d
) is the output Q of the D flip-flop 11 which is the gate signal.
1, and (e) shows the sawtooth wave generated by the sawtooth wave generator and the level of the comparison signal for setting its peak voltage. (f) is the first bold-off signal (
Hol), and (CI> is the second hold-off signal (H
O2>, (h) shows the output Q4 of the D flip-flop 14, and (1) shows the knot Q3 of the D flip-flop.
Showing the output.

Figure 2 shows a case where the period of the trigger pulse P applied to the input terminal 30 is sufficiently shorter than the period of the second hold-off signal HO2 shown in (e). .

The trigger signal shown in Figure 2 (a>) is ORed from input terminal 3Q.
When applied through the gate 27, the up edge of the trigger pulse PIA shown in (b) is output from the OR gate 27 and the D shown in (C') which was previously "L II"
The output Q2 of the flip-flop 12 becomes “Hvt” and D
Since the data terminal D1 of the flip-flop 11 is set to "H", the application of the next up edge of the trigger pulse P2A causes the gate output Q1 of the D flip-flop 11 shown in (d) to become "HIT", and as shown in (e). generates a sawtooth wave as shown, and resets the reset terminal R of the D flip-flop 14.
4 and makes its output Q4 shown in (h) "L". The output Q1 shown in (d) is applied to one input terminal of OR gates 21 and 27, so that this During the period when the output Q1 is "i", the trigger signal applied to the input terminal 30 has no effect on the D flip-flop 11.

When the sawtooth wave in (e) reaches the level of the comparison signal,
The second hold-off signal 1-102 shown in (CI>) and the first hold-off signal HO1 shown in (f) should be output.
H79), output Q1 of (d) is "Lpa", and (e)
, the sawtooth wave is terminated, and the output Q2 shown in (C) is set to "L 99."

When the up edge of the trigger pulse P3A shown in (b) is applied to the clock input terminal CK4 of the D flip-flop 14 via the OR gate 24, the output Q4 shown in (h) becomes "HIf".

In this state, even if a subsequent trigger pulse P is applied, the D terminal D1 of the D flip-flop 11 is (C
), the output Q1 is “H” because it is “L 11”.
However, the first hold-off signal HOI shown in (f) determined by the circuit constants
When the period ``'' ends and the level becomes ``L,'' the reset terminal R2 of the D flip-flop 12 becomes ``L If'' and the reset is released, so the next input trigger pulse PIB shown in (b) The up edge is OR gate 22
When the clock signal is applied to the clock input terminal OK2 via the clock input terminal OK2, the output Q2 becomes "H" in response immediately.

In this state, the data terminal D] of the D flip-flop 11 is "H99", and the first hold-off signal HO
1 has ended, the reset terminal R1 is “L H
Roughly speaking, since the output Q1 is "LH", one input terminal of the OR gate 21 remains "L", and if the trigger pulse P2B is applied to the other input of this OR gate 21, then If so, immediately send a gate signal @ (Ql to “H”).
In other words, the standby state is the state in which you can obtain the

In this way, the next trigger pulse P2B is applied in the standby state created by the trigger pulse PIB, so the D flip 70 knob 11 operates without jitter, and the output Q1 shown in (d> Please output “′H゛°
) and (e) to stably generate the sawtooth wave without jitter. The subsequent operation is based on the trigger pulse P IA"'
The same is true for P 3A.

In this way, if the period of the trigger pulse P is shorter than the period of the second holdoff signal HO2 (“period of H9m”), no jitter occurs.

Next, the trigger pulse P is the first holdoff signal HO1
The operation in the case where the voltage is applied at the same time as the termination of the voltage will be explained with reference to FIG.

Trigger pulse P shown in FIG. 3(b). When the up edge of is output from the OR gate 27, the output Q1 of (d)
becomes "HIt" and outputs a gate signal, generating the sawtooth wave shown in (e). When it reaches the level of the comparison signal, the second hold-off signal 1-(02('
“H”) and the first hold-off signal HO shown in (f)
1 (set to "Hpe"), terminate gate output Q1 shown in (d) (set to "LD"), and output Q2 to "
Make it L II.

After a period of time determined by the circuit constant, the first holdoff signal HO1 is completed and becomes “L”), and at the same time (b
Even if the up edge of the trigger pulse P1 shown in ) is applied, the data terminal D1 is at "H" at that time, so the D flip-flop 11 does not operate and no gate signal is output, as shown in (d). Output Q1 remains at "1 u".

At this time, the set terminal S2 of the D flip-flop 12 is "L 19", the first hold-off signal H01 is connected to the reset terminal R2, and it is in a transient state from "Hu" to "H", so the output For example, Q2 sometimes transitions to "Hme" with a "JITSU/YOU" as shown in (C).

Since the data terminal D4 of the D flip-flop 14 is always held at "HIt," the output Q4 also changes to "Hme" upon application of the up edge of the trigger pulse P1.
becomes. Shortly thereafter, the second holdoff signal)
-102 shifts to L'' as shown in (Q).

In this state, the reset terminal R1 of the D flip-flop 11 is "L tt" as shown in (f>), the data terminal D1 is "H" as shown in (C), and (
Since the output Q1 is "H" as shown in d), if the next trigger pulse P2 is applied to the other input terminal of the OR gate 21 which has been applied to one input terminal, the output Q1 is "H". The output Q1 becomes "Hu" and is in a state in which a gate signal can be obtained, that is, in a standby state.

Then, the trigger pulse P2 shown in (b) is applied to the OR gate 2.
7, the gate signal shown in (d) is output without jitter (Ql becomes "HII").As a result, the sawtooth wave shown in (e) is output.This output Q
1, the output Q4 shown in (h) becomes “
Become L II. Here, the D flip-flop 13 is
As shown in (Q), the data terminal D3 is “L” and (
Since the output Q4 shown in h) is "H" and is applied to the other input terminal of the OR gate 23, it will not operate due to the up edge of the trigger pulse P2 applied to one input terminal. (i) ω knot Q3 output remains “H”.

When the sawtooth wave shown in (e) reaches the level of the comparison signal, the second hold-off signal HO2 (“'H”) shown in (g)
Then, the first hold-off signal @HOI in (f) should be generated to “Htp”, and the output Q2 in (C) should be reset to “
To terminate the gate signal in (d), set the output Q1 to "L H") and terminate the sawtooth wave in (e).Here, the knot Q3 output shown in (i) is the trigger pulse P. Unless the period of "L t
It remains t.

On the other hand, the 02 output of (C) may remain at "L u", but in this case, the Q2 output of (C) becomes H09 due to the trigger pulse P2 of (b), and the trigger pulse of (b) - The Q1 output in (d) becomes "H" at pulse P3.

Since it operates in this way, the first hold-off signal HO1
Even if the trigger pulse P1 is input at the same time as the end of the trigger pulse P1, the gate signal will not be obtained and the standby state will only be created, and the gate signal will be obtained by the next trigger pulse P2, so jitter will not occur. do not have.

A case in which the cycle of the trigger signal becomes longer midway through and the next trigger signal is applied after the second hold-off signal H02 ends will be described with reference to FIG. 4A.

When the up edge of the trigger pulse P1 shown in FIG. 4A (b) is applied, the output Q2 in (C) becomes "H'",
When the next up edge of trigger pulse P2 is applied, the output Q1 shown in (d) becomes "Hu" and generates the sawtooth wave shown in (e).

When this reaches the level of the comparison signal, the second hold-off signal HO2 (set to “HI”) in (g) and (f)
To generate the first hold-off signal 1-101 of “H1m
), which makes the gate output Q1 in (d) “L”,
(e) End the sawtooth wave. The first hold-off signal HO1 in (f) ends and becomes "L 11", and a little later, the second hold-off signal H02 in (q) also ends and becomes "L II)," as shown in (b). The up edge of trigger pulse P3 is input.

At this time, the D terminal D1 of the D flip-flop 11 is (C>
As shown in the figure, since it is at "°L", there is no output of the gate signal. The knot Q3 output shown in (i) and the output Q2 shown in (C) which are applied to the first holdoff HO1 shown in (f) and the set terminal S2 are both in the "'L" state, and here ( Since the up edge of the trigger pulse P3 shown in b) is input, the output Q2 shown in (C) becomes "HIT". At the same time, the not Q3 output in (1) also becomes "Htt". The output in (C) When Q2 becomes Hpp, this Htt is applied to the clock terminal GK2 of the D flip-flop 12 via the OR gate 22, and (
Since "Hee" of the output of the knot Q3 in i) is applied to the set terminal S2, the output Q2 of (C) is held at "Hpp".

In this state, the reset terminal R1 of the D flip-flop 11 is "1" as shown in (f), and the output Q1 in (d) is "L", so that the standby state is established.

The up edge of the next trigger pulse P4 shown in (b) is applied there, and the output Q1 in (d) is “HI” without jitter.
At t, a sawtooth wave as shown in (e) is generated, and when it reaches the level of the comparison signal, the second hold-off signal HO2 (set to "H") shown in (q) and the first hold-off signal shown in (f) are generated.
Generate hold-off signal HO1 (set it to “H”)
Terminate the sawtooth wave in (e).

When the period from when a trigger signal is applied until when the next trigger signal is applied remains larger than the second hold-off signal HO2, the operation is performed as shown in FIG. 4B.

When the up edge of the trigger pulse P1 in (b) is applied after the termination of the second hold-off signal H02 in (q) generated by the trigger pulse P0, not shown in (b), the D flip-flop 11 is in the standby state, so it outputs the gate signal immediately without jitter,
The output Q1 in (d) becomes "H99" and generates the sawtooth wave shown in (e), and when it reaches the level of the comparison signal, it outputs the second hold-off signal HO2 shown in (g). "Hee>", the first hold-off signal 1 "01" shown in (f) is output ("Hu"), which causes the output Q1 to go "L to" and terminate the gate signal, and the sawtooth wave shown in (e) is also output. Let it end. When the first hold-off signal H01 shown in (f) is generated (becomes H99), the reset terminal R2 and the set terminal S2 become "H" at the same time, so the output Q2 is either "Hu" or "L tt". However, the first state shown in (d)
At the same time that the hold-off signal HO1 ends (becomes "Lvt"), the output Q2 shown in (C) is determined to be "H'',
The standby mode is entered and the operation continues without jitter even in response to the next trigger pulse P2.

Here, when the trigger pulse P1 in (b) is applied,
The reset terminal R4 of the D flip-flop 14 is “L e
t, the output Q4 is “
However, this trigger pulse P1 also causes the output Q1 in (d) to become "'H", which resets the reset terminal R4 of the D flip-flop 14.
The output Q4 of h) immediately becomes "LP?", causing a glitch.

This glitch is applied to one terminal of the OR gate 23 connected to the clock terminal CK3 of the D flip-flop 13, but the other terminal is applied to the OR gate 23 of (b).
Since the output "H" of the gate 27 is applied, it is gated and this glitch has no effect.

The operation when the period of the trigger pulse P changes and becomes shorter and the trigger pulse is applied simultaneously with the end of the first hold-off signal HOI will be described with reference to FIG.

The first hold-off signal HO1 shown in (f) is generated (becomes "H") by the operation based on the previous trigger pulse Po (not shown) in FIG. 5(b), and the trigger pulse P The cycle suddenly becomes shorter and the HOI ends (
When the trigger pulse P1 of (b> is applied at the same time as "L"), in order to receive this trigger pulse P1 before the voltage of the reset terminal R1 of the D flip-flop 11 is sufficiently stabilized, Various cases arise.

Immediately before the trigger pulse P1 shown in (b) is applied, "H" is applied to both the set terminal S2 and reset terminal R2 of the D flip 70 knob 12, so the output shown in (C) Although Q2 is uncertain,
If the output Q2 is "H", the device shifts to the standby state at the same time as the first hold-off signal F-101 (f) ends.

When the trigger pulse P1 (b) is applied in this transient state transitioning to the standby state, the voltage at the reset terminal R1 is not stable enough, so that , (d) may cause jitter. The sawtooth wave shown in (e) generated by this also causes jitter as shown by diagonal lines. Until this trigger pulse P1 is applied, R4 is "L tt" as shown in (d), and the data terminal D4 of the D flip-flop 14 is always "'H", so the output Q4 is "' H
'', but the output Q1 shown in (d) is the trigger pulse P
1 becomes "T1", the reset terminal R4 becomes "H" and is reset.
Output Q4 is immediately returned to "LIT".

When the sawtooth wave shown in (e) reaches the level of the comparison signal, it generates the already completed second hold-off signal HO2 shown in (g) and the first hold-off signal shown in (f). ), which makes the gate output Q
1 is terminated (set to "L tt"), and the sawtooth wave shown in (e) is terminated.

(When the first hold-off signal HO1 shown in f> becomes Hu, the not Q3 output is already “U PI, so
The output Q shown in (C) was undefined (ND>) until the application of
2 becomes “L wl.

Simultaneously with the termination of the first hold-off signal HOI (Hol becomes "L ty") shown in (f) resulting from the trigger pulse P1, the trigger pulse P2 is applied as shown in (b). , since Q2 shown in (C) is "L 99", there is no output of the gate signal in (d), and the output Q4 in (h) and the output Q2 in (C) are changed to HPI, and (C) The output Q2 of may remain at L11. When the output Q2 of (C) changes to "'H", Dl
is "H", R1 is "'L", and Ql is "L It", so the standby state is reached, and if the output Q2 remains at "L tp", the output Q2 becomes "He" by the next trigger pulse P3.
t and goes into standby mode.

In this standby state, when the next trigger pulse P3 (or R4, not shown) is applied as shown in (b), it changes the gate output Q1 to 11 HPl without jitter.
As a result, the sawtooth wave shown in (e) is generated,
Output Q4 is reset to "L". Eventually, the sawtooth wave in (e) reaches the level of the comparison signal, and the second hold-off signal @H02 shown in (g>) and the first hold-off signal HO1 shown in (f) are generated (set to "HIF"),
The output Q1 shown in (d) is terminated (set to "L It"), and the sawtooth wave shown in (e) is terminated. No jitter occurs for the subsequent input of the trigger pulse P.

On the other hand, with the trigger pulse P1 shown in (b), the output Q1 shown in (d) may not become "Hpe" but remain at "LIT". In this case, no sawtooth wave is generated, and the not Q3 output shown in (i) shifts from "HPI" to "L" and enters the standby state.Then, the next trigger pulse P
2, the output 01 of (d) shifts from L pt to "HH" and stably generates a sawtooth wave.

Just before the trigger pulse P1 in (b) is applied, (C
) in a transient state where the output Q2 shifts to "L",
When the trigger pulse P1 in (b) is applied, the output Q1
maintains “L to”, but the not Q3 output of (i) becomes “L”, and sets the set terminal S2 of the D flip-flop 12 to “L”. However, the D flip-flop 12
The first hold-off signal HOI in (f) connected to the reset terminal R2 may become LIF just before the set terminal S2 of 02 output becomes “H99”
Whether it becomes L Pl is uncertain.

Next, the first holdoff signal 1-101 in (f) is
To Shun who has moved to L II, or gate 2 shown in (b)
The case where the trigger pulse itself, which is the output of 7, is input will be explained.

The first hold-off signal HO1 shown in FIG. 5(f) is low.
When it comes to IT, the output Q2 of (C) becomes the knot Q3 of (i)
The “H” output causes a transition from “L” to “HIT”. In the transient state of this transition, when trigger pulse P1 is applied, output Q1 in (d) generates jitter and becomes “L”.
When I becomes “H”, the output Q1 in (d) is “L”
02 in (C) may go into a standby state, such as -“HIt”.

This (f) first holdoff signal 1-101 is “L”
11, and the output Q2 of (C) is changed from “L pe” to “HI”
Transition to F (knot Q3 output of i> is 11 H#
In the transient state transitioning from # to “L pt, (b)
When the trigger pulse P1 of (c) is applied, the output Q of (c)
2 is about to change from "L" to "HIt", but may change to "[-" again before it becomes sufficiently "H".

In this way, the timing of applying the trigger pulse P1 in (b) causes jitter in the output Q1 in (d), and (e)
Sawtooth waves can also cause jitter, but such jitter occurs only once due to trigger pulse P1, and after that, the notation Q3 output in (1) changes from “HIf” to “L re Therefore, no jitter occurs depending on the trigger pulse P applied thereafter. (f) First hold-off signal HOI
becomes “H” from “L”, the output Q2 of (C)
is always reset and becomes “LIT”, so this first
At the end of the hold-off signal HO1, that is, "'H''
In the transient state in which the transition from "L'' to No jitter due to applied trigger pulse P3 (d)
The output Q1 can be obtained.

A case will be described with reference to FIG. 6 in which the period of the trigger pulse P suddenly changes from a short state to become longer, and the trigger pulse is applied at the same timing as the end of the second hold-off signal HO2.

The second hold-off signal shown in (Q) generated by the synchronized short trigger pulse Po shown in FIG. 6(b))
When the trigger pulse P1 is applied when the trigger pulse P1 ends (< 11 L 99), the output Q2 shown in (C) is low immediately before the application.

Therefore, Dl is “L” and no gate signal can be generated, and the data terminal D of the D flip-flop 13
3 takes the value of either “1” or “L H,
Data terminal D4 of D flip-flop 14 is always “H”
Therefore, the output of the knot Q3 takes either "H" or am Let as shown in (i), and the output of the knot Q4 becomes "HIn" as shown in (h). However, since the output Q2 shown in C) becomes 14 H11, the standby state becomes (R1 is "S", Ql is "'L">, and by the application of the next trigger pulse P2, it becomes (d>). The gate output Q1 shown can be stably obtained without jitter (becomes "H91").

This generates a sawtooth wave shown in (e>) and resets the output Q4, which was at "H", to "L tt".

Here, even if the not Q3 output shown in (i> becomes "H" or "L" due to the application of the trigger pulse P1, the output Q2 shown in (C) becomes "H". Because it will be,
There is no direct relationship to the gate output Q1 in (d).

When the sawtooth wave shown in (e) reaches the level of the comparison signal, it generates the second hold-off signal shown in (CX>) and the first hold-off signal H01 shown in (f).
1), the gate output Q1 in (d) is set to "L" to terminate the sawtooth wave shown in (e), and the reset terminal R2 and set terminal S2 of the D flip-flop 12 are set to "L".
(b> trigger pulse P1 is applied, (i)
When the knot Q3 output of becomes "H'', it becomes "H" as shown in (f> and (i), respectively, so
The output Q2 in (C) becomes undefined (ND), but when the first hold-off signal H01 shown in (f) becomes "L", the output Q2 becomes undefined (ND).
2 is set to “Het” and the standby state is set (R1 is “L”).
", Dl is "H", Ql is "L"), and when the next trigger pulse P3 is applied, the gate output Q1 shown in (d) is generated without jitter.

On the other hand, when the trigger pulse P1 in (b) is applied, if the nott Q3 output of (i> becomes "L" level, (C
The output Q2 of ) is reset to "L IF" when the first hold-off signal H01 of (f> is generated. In this state, when the trigger pulse P3 of (b) is applied, the output Q2 of (d
) remains at “L me,” and the output Q1 of (C) remains at “L me.”
2 becomes "Hte" and enters the standby state. The not Q3 output of (i) becomes "L" due to the timing of trigger pulse P3.
tt and stays at H99, which results in an undefined state (ND), but in the case of 'H', the first hold-off signal HOI in (f) changes from 'H99 to 'L et
With one trigger pulse applied when the level has stabilized sufficiently, the first hold-off signal)01 becomes "L" and the applied trigger pulse - A jitter-free sawtooth wave can be generated using a pulse followed by another trigger pulse.

In the above explanation, the recovery of the second holdoff signal H02 only needs to be delayed by, for example, 10 nS or several Qns from the trailing edge of the first holdoff signal 1-(01, so the sawtooth wave generator 18 Inside the
can easily occur.

Since only one input terminal of the OR gate 24 in FIG. 1 is used, it may be omitted and the trigger pulse P may be directly applied to the clock input terminal CK4.

In the above explanation, as soon as the sawtooth wave reaches the comparison signal shown in (e> in FIGS. 2 to 6), (f
) and l) first and second hold-off signals HO1
, HO2, which causes the output Q1 in (d) to be “L”.
The sawtooth wave shown in (e) is terminated at ``.''. Therefore, for convenience of explanation, it is shown that some time elapses from the intersection of the sawtooth wave with the comparison signal in (e) until the peak voltage is reached, but in reality,
Almost no time passes from when the comparison signal and the sawtooth wave intersect until the peak voltage is reached, and the level of the comparison signal and the peak voltage of the sawtooth wave almost always match.

[Effect of the invention] As is clear from the above explanation, according to the present invention,
If a trigger pulse is applied during a period that could cause direct jitter after the end of the first holdoff signal, the trigger pulse may cause the gate signal to not be generated, thereby preventing the occurrence of jitter. If the present invention is used in a high-performance cathode ray tube oscilloscope or sampling oscilloscope,
The effect is extremely large.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing one embodiment of the present invention. Time charts when the cycle and timing of the trigger pulse applied to the circuit are variously changed. Figures 7 and 9 are circuit configuration diagrams showing conventional examples, and Figures 8 and 10 are , are the time charts of FIGS. 7 and 9, respectively. 11-16...D flip-flop 17...Retriggerable one-shot multivibrator 18.19...Sawtooth wave generator 21 27...OR gate 30...Input terminal.

Claims (2)

[Claims] (1) In the standby state, a gate signal for generating a sawtooth wave is generated by applying a trigger pulse obtained from a trigger signal, and furthermore, even if a trigger pulse is applied thereafter, the gate signal remains unchanged for a predetermined period. generating a first hold-off signal for inhibiting the action of the first hold-off signal; and a second hold-off signal ending a little predetermined time later than the end of the first hold-off signal; After the completion of the second
If a trigger pulse is applied before the hold-off signal ends, this trigger pulse creates the standby state, and the next pulse generates a gate signal, and during the generation period of this gate signal, the trigger signal A synchronization method characterized in that the application of the trigger pulse is prohibited despite the application of the trigger pulse. (2) a first flip-flop means having a reset terminal, which receives the edge of the trigger pulse and outputs a gate signal at the level applied to the D1 terminal; and receives the edge of the trigger pulse; A second flip-flop that outputs a constant level that is always applied to the D2 terminal, does not operate depending on the edge of a trigger pulse that is subsequently applied during this output period, and has a set terminal and a reset terminal. third flip-flop means for not outputting the level being applied to the D3 terminal when the edge of the trigger pulse or one other input is applied; fourth flip-flop means having a reset terminal for outputting a constant level that is always applied to the D4 terminal; and only during a period when a trigger signal is input and there is no gate signal, the trigger signal is set to the trigger pulse. a first hold-off signal having a predetermined period due to the generation of the sawtooth wave; sawtooth wave generating means for generating a second hold-off signal that ends a predetermined time later than the end of the hold-off signal, and applying the first hold-off signal to a reset terminal of the first flip-flop means. and applying the output of the second flip-flop means to the D1 terminal, applying the first hold-off signal to the reset terminal of the second flip-flop means, and applying the first hold-off signal to the set terminal of the second flip-flop means. The output of the fourth flip-flop means is applied as the other input of the third flip-flop, and the second hold-off signal is applied to the D3 terminal, respectively. A synchronous circuit characterized in that a gate signal which is an output of the first flip-flop means is applied to the reset terminal of the four flip-flops.