JPH0197018A - Signal generating circuit - Google Patents
Signal generating circuitInfo
- Publication number
- JPH0197018A JPH0197018A JP62255354A JP25535487A JPH0197018A JP H0197018 A JPH0197018 A JP H0197018A JP 62255354 A JP62255354 A JP 62255354A JP 25535487 A JP25535487 A JP 25535487A JP H0197018 A JPH0197018 A JP H0197018A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- output
- circuit
- difference
- phase difference
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は信号発生回路に関し、特に2つの信号の同期の
確立に改良を加えて目標とする周波数を速やかに得られ
る信号発生回路を提案するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a signal generation circuit, and in particular proposes a signal generation circuit that can quickly obtain a target frequency by improving the establishment of synchronization between two signals. It is something.
第4図は従来の位相同期ループのブロック図であり、入
力信号(ノー<ルス信号)■S及びフィードバック信号
(パルス信号狂BSを入力とする位相比較器1は再入力
信号の位相差に相当するパルス信号を出力し、この出力
信号はローパスフィルタ2に入力されて位相差に相当す
る電圧信号がローパスフィルタ2から出力され、この電
圧信号は電圧制御発振器(VCO) 3へ入力されVC
O3はこの入力信号の電圧に応じた周波数のパルス信号
を出力する。Figure 4 is a block diagram of a conventional phase-locked loop, in which a phase comparator 1 whose input is an input signal (norse signal) S and a feedback signal (pulse signal error BS) corresponds to the phase difference of the re-input signal. This output signal is input to a low-pass filter 2, and a voltage signal corresponding to the phase difference is output from the low-pass filter 2. This voltage signal is input to a voltage controlled oscillator (VCO) 3 and is input to the VC
O3 outputs a pulse signal with a frequency corresponding to the voltage of this input signal.
この出力信号OSは分周器4でN分周され、分周出力を
前記フィードバック信号FBSとしている。This output signal OS is frequency-divided by N in a frequency divider 4, and the frequency-divided output is used as the feedback signal FBS.
このような構成の回路では入力信号IS及びフィードバ
ック信号FBSの位相差が大きい場合は系の応答は振動
的になり易く、このために安定な同期状態を迅速に得る
ことが難しいという問題点がある。In a circuit with such a configuration, if the phase difference between the input signal IS and the feedback signal FBS is large, the response of the system tends to become oscillatory, which poses a problem in that it is difficult to quickly obtain a stable synchronized state. .
本発明は斯かる問題点を解決するためになされたもので
あって、位相比較器が出力する位相差又は周波数差の履
歴を利用することにより振動を抑制して同期状態を速や
かに得ることができる信号発生回路を提供することを目
的とする。The present invention has been made to solve this problem, and it is possible to suppress vibration and quickly obtain a synchronized state by using the history of the phase difference or frequency difference output by the phase comparator. The purpose is to provide a signal generation circuit that can
c問題点を解決するための手段〕
本発明に係る信号発生回路は、人、出力両信号の位相差
又は周波数差に関連する信号、その履歴に関連する信号
及び位相差又は周波数差の時系列的変化量に関連する信
号の和を演算し、この演算出力を出力信号の制御信号と
する。Means for Solving Problem c] The signal generation circuit according to the present invention generates a signal related to a phase difference or a frequency difference between human and output signals, a signal related to the history thereof, and a time series of the phase difference or frequency difference. The sum of signals related to the amount of change in the target is calculated, and the calculated output is used as a control signal for the output signal.
上述の和は位相差又は周波数差の補正を抑制するように
作用し、その結果振動が抑制されることになる。The above-mentioned sum acts to suppress the correction of the phase difference or the frequency difference, and as a result, vibrations are suppressed.
〔実施例〕″
以下本発明をその実施例を示す図面に基づいて詳述する
。[Examples]'' The present invention will be described in detail below based on drawings showing examples thereof.
第1図は本発明に係る信号発生回路のブロック図である
。位相比較器1には出力の目標とする入力信号(パルス
信号) Is及び出力信号O8のフィードバック信号F
BSが入力され、両者の位相差又は周波数差に相当する
パルス信号、即ち位相差信号又は周波数差信号を演算器
6及び履歴保持回路5へ入力させる。履歴保持回路5は
位相差信号Δφを順次ホールドする保持回路51及びこ
れが保持した位相差信号Δφをi個分累算する累算回路
52を備え累算回路52はΣΔφ直に相当する信号を演
算器6へ発する。FIG. 1 is a block diagram of a signal generation circuit according to the present invention. The phase comparator 1 receives the target input signal (pulse signal) Is and the feedback signal F of the output signal O8.
BS is input, and a pulse signal corresponding to the phase difference or frequency difference between the two, that is, a phase difference signal or a frequency difference signal, is input to the calculator 6 and the history holding circuit 5. The history holding circuit 5 includes a holding circuit 51 that sequentially holds phase difference signals Δφ and an accumulation circuit 52 that accumulates i phase difference signals Δφ held by this holding circuit 51. The accumulation circuit 52 calculates a signal directly corresponding to ΣΔφ. Emit to vessel 6.
保持回路51出力は変化量算出器7へ入力され、変化量
算出器7は現在のΔφと、lサンプルタイミング前のΔ
φとの差を算出し、これを演算器6へ与える。The output of the holding circuit 51 is input to the change amount calculator 7, and the change amount calculator 7 calculates the current Δφ and Δ1 sample timing before.
The difference with φ is calculated and given to the arithmetic unit 6.
演算器6は3つの入力、つまり位相比較器1出力と、履
歴保持回路5又は累算回路52出力と、変化量算出器7
の出力とを加算し、これに相当する電圧信号を出力する
。この電圧信号はVCO3へ与えられ、その結果VCO
3は前記電圧信号に相応する周波数の出力信号(パルス
信号)OSを発する。The arithmetic unit 6 has three inputs: the output of the phase comparator 1, the output of the history holding circuit 5 or the accumulation circuit 52, and the change amount calculator 7.
and the output of , and a voltage signal corresponding to this is output. This voltage signal is applied to VCO3, resulting in VCO
3 emits an output signal (pulse signal) OS having a frequency corresponding to the voltage signal.
この出力信号O3は分周器4でN分周されてフィードバ
ック信号FBSとして位相比較器1へ与えられる。This output signal O3 is frequency-divided by N by a frequency divider 4 and given to the phase comparator 1 as a feedback signal FBS.
次にこのような回路による場合に振動が抑制されること
について説明する。Next, it will be explained how vibrations are suppressed using such a circuit.
第3図は第4図に示す従来回路における出力信号又はフ
ィードバック信号の時間的変化を示す特性図であり、直
線で示す目標値の位相との差a。FIG. 3 is a characteristic diagram showing temporal changes in the output signal or feedback signal in the conventional circuit shown in FIG. 4, and shows the difference a from the phase of the target value shown by the straight line.
b等がVCO3の制御信号となる。b etc. become control signals for the VCO3.
この差は制御の都度更新されるものであるので目標値に
漸近するまでに振動系に入ってしまうの。Since this difference is updated each time the control is performed, it enters the oscillating system before it asymptotically approaches the target value.
である。It is.
第2図は本発明回路の対応する特性図である。FIG. 2 is a corresponding characteristic diagram of the circuit of the invention.
図に示す破線の如く出力信号又はフィードバック信号が
変化するものとすると、1n−IN t、1での位相
差信号はΔφ、−1.Δφ7となる。第4図の回路では
Δφゎだけを用いるのであるが、本発明回路ではΔφ7
と、Δφ、−Δφa−1と、Δφ7゜Δφ7−1・・・
の累算値とを加えたものを用いる。その結果Δφ7によ
る補正よりも小さい補正が行われることにより結果的に
は第2図に実線で示す如く振動なしに又は小さな振動で
目標値へ漸近していく。Assuming that the output signal or feedback signal changes as shown by the broken line in the figure, the phase difference signal at 1n-IN t,1 is Δφ, -1. It becomes Δφ7. In the circuit of FIG. 4, only Δφゎ is used, but in the circuit of the present invention, Δφ7
, Δφ, -Δφa-1, Δφ7゜Δφ7-1...
The cumulative value of As a result, a smaller correction than the correction by Δφ7 is performed, and as a result, asymptotically approaches the target value without vibration or with small vibration, as shown by the solid line in FIG.
なお履歴保持回路5.変化量算出器7はアナログ回路、
ディジタル回路のいずれによっても構成できる。Note that the history holding circuit 5. The change amount calculator 7 is an analog circuit,
It can be constructed using any digital circuit.
本発明の回路は以上のように位相差1周波数差の履歴を
保持してこれを発振周波数制御に反映させるので、位相
差9周波数差の補正が抑制され、その結果振動も抑制さ
れ、速やかに目標値に達する。従って応答性の高い信号
発生回路が実現できる。As described above, the circuit of the present invention retains the history of the phase difference 1 frequency difference and reflects this in the oscillation frequency control, so the correction of the phase difference 9 frequency difference is suppressed, and as a result, vibrations are also suppressed and the Reach target value. Therefore, a signal generating circuit with high responsiveness can be realized.
第1図は本発明のブロック図、第2図はその動作説明の
ための特性図、第3図は従来回路の特性図、第4図は従
来回路のブロック図である。
1・・・位相比較器 3・・・VCO4・・・分周器5
・・・履歴保持回路 7・・・変化量算出器51・・・
保持回路 52・・・累算回路蛙お、図中、同一符号は
同一、又は相当部分を示す。
代理人 大 岩 増 雄
芥 2 ■
1!1間
第3ΣFIG. 1 is a block diagram of the present invention, FIG. 2 is a characteristic diagram for explaining its operation, FIG. 3 is a characteristic diagram of a conventional circuit, and FIG. 4 is a block diagram of the conventional circuit. 1... Phase comparator 3... VCO4... Frequency divider 5
...History holding circuit 7...Change amount calculator 51...
Holding circuit 52...Accumulation circuit In the figures, the same reference numerals indicate the same or corresponding parts. Agent Masu Oiwa Yuke 2 ■ 1!1 3rd Σ
Claims (1)
又は周波数差を時系列的に検出して両信号の同期をとる
構成とした信号発生回路において、前記入力信号及び出
力信号の位相差又は周波数差の履歴を保持する回路と、
位相差又は周波数差の時系列的変化量を算出する回路と
、前記履歴に関連する信号、前記変化量に関連する信号
及び位相差又は周波数差に関連する信号の和を演算する
回路とを具備し、該回路の出力を出力信号の制御信号と
していることを特徴とする信号発生回路。1. In a signal generation circuit configured to synchronize the two signals by detecting the phase difference or frequency difference between the input signal and the fed-back output signal in time series, the phase difference or frequency difference between the input signal and the output signal is detected. A circuit that maintains the history of
A circuit that calculates the amount of change over time in the phase difference or frequency difference, and a circuit that calculates the sum of a signal related to the history, a signal related to the amount of change, and a signal related to the phase difference or frequency difference. A signal generating circuit characterized in that the output of the circuit is used as a control signal for an output signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62255354A JPH0197018A (en) | 1987-10-09 | 1987-10-09 | Signal generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62255354A JPH0197018A (en) | 1987-10-09 | 1987-10-09 | Signal generating circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0197018A true JPH0197018A (en) | 1989-04-14 |
Family
ID=17277622
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62255354A Pending JPH0197018A (en) | 1987-10-09 | 1987-10-09 | Signal generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0197018A (en) |
-
1987
- 1987-10-09 JP JP62255354A patent/JPH0197018A/en active Pending
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