JPH0197660A - Recorder - Google Patents

Abstract

PURPOSE:To increase productivity and decrease manufacturing cost by providing drive means which are located on either side of a recording head and receive mutually different signals to have their cascade connections opposed to each other. CONSTITUTION:When an external terminal REV is at LOW, a drive LSI 160 operates in a conventional manner to receive record date from a data terminal D1 and shift the data from its data terminal D2 to the next drive LSI 160. With the terminal REV at HIGH, on the other hand, record data are received through the data terminal D2 and shifted to the next LSI 160 through the terminal D1. Therefore, when drive LSIs 160 are cascaded, the data input and output terminals are D1 and D2, respectively, with REV at LOW. This relation is reversed with REV at HIGH, that is, D2 is the data input and D1 is the data output.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a recording device such as an optical printer, and more particularly to a drive circuit mounted on a control board for a recording element.

[Prior art and its problems]

In page printers such as liquid crystal printers, LED printers, thermal printers, and electrostatic recording printers, recording elements such as liquid crystal shutters (LC3), light emitting diodes (LEDs), heat-generating heads, and multi-styli are arranged in a row, and the recording Recording is performed by driving the elements based on recording signals.

Hereinafter, the configuration of the main parts according to the present invention of a conventional liquid crystal printer using a liquid crystal light shutter as a recording element will be briefly described.

First, FIG. 16 shows a drive circuit for a conventional two-time division liquid crystal optical shutter stored in an optical recording head in an optical printer. Note that the circuit shown in FIG. 16 is a block diagram of an LSI circuit composed of 0M03 circuits,
The circuit shown as 1 in the figure is the entire circuit of one LSI. This LSI can be cascaded, so this LSI
This configuration uses a plurality of Is to drive all the micro shutters. Also, if the circuit shown as lO in the figure is one channel, one LSI has 256
It has a channel circuit.

The one-channel circuit 10 mainly includes a shift register 11 for taking in recording data, delay sections 13 and 14 for delaying data from this shift register, the shift register 11, the data of the delay section 13, and the shift register 11. It has data latch sections 12 and 15 for latching direct data from the respective micro shutters, and further includes drive signals PTI for each micro-shutter of the liquid crystal light shutter.
It also includes a data selector modulator 16 for selecting PT2, a level shifter 17, an inverter 18, and a high voltage output buffer 19. The latch pulse generator 2o is composed of three master-slave flip-flops 2122.23 and three Nant gates 24, 25, and 26, and generates three-phase latch pulses CK21, CK22, and CK23. T1.12 Human power is partially controlled by external control 13
．． By setting T1 to H level, data delay due to delay part 14 is controlled, and by setting T2 to H level, data delay by delay part 14 is controlled.
Data delay caused by 3 is eliminated. This is to perform time-division driving in accordance with the arrangement intervals of the micro-shutters arranged in a staggered manner in the liquid crystal light shutter (hereinafter referred to as LC3). Different types of liquid crystal light shutters are driven in the same way.
It can be controlled by l.

Recorded data is clock pulse CKIA (CK1/B)
It is serially input to the D terminal in synchronization with the rising edge of the clock pulse CKIA (CKIB), and taken into the shift register 11 in synchronization with the falling edge of the clock pulse CKIA (CKIB). When 1947 minutes of recorded data is captured, the latch pulse generator 2
Latch pulses CK21, 22, and 23 are sequentially output from CK0.

(TI=T2=L level). As a result, the data in the shift register 11 is latched into the delay section 14 or directly into the data latch section 15. Therefore, while the data in the odd-numbered shift registers 11 is directly latched into the data latch unit 15, the shift register 11 is in a waiting state for receiving the video signal of the next line. Furthermore, among the recording data for one line, the final stage shift register 11
The data exceeding the above is taken in to the shift register of the next stage and subsequent LSIs via the cascade output buffer 30.

The detailed circuit configuration of the data selector modulation section 16 is described in the first section.
7(a) shows a detailed circuit configuration of the delay section 13.14 and data latch section 12.15, FIG. 17(b) shows a detailed circuit configuration of the shift register 11, and FIG. 17(C) shows a detailed circuit configuration of the shift register 11.

Next, FIG. 18 is a diagram showing a circuit configuration of a recording control section 40 in an optical recording head using the driving LSII.

The liquid crystal light shutter 50 includes a signal electrode 51 and a common electrode 52.
-1 and 52-2, microshafts 53-1 and 53-2 are arranged in a staggered manner. In the liquid crystal light shutter 50, the signal electrodes 51 are alternately drawn out in opposite directions, and the signal electrodes 51 are connected to a driving LSI.
A drive signal for two-time division drive is driven from I. Further, the common electrodes 52-1 and 52-2 are supplied with a selection signal CO via the high voltage driver 54 to select the microshutter on the a column or the microshutter on the b column.
MI and C0M2 are applied. Here, a cross-sectional view of the optical recording head 60 is shown in FIG. 19. In the optical recording head 60 shown in FIG. 19, the signal electrode of the liquid crystal optical shutter 50 is
Circuit boards 62.6 provided on both sides of the lamp case 61
It is connected to a conductive pattern 2' (not shown) by a film electrode connector 63 which is a flexible connector.

Further, the conductive pattern on the circuit board 62, 62' is
It is connected to the drive signal output electrode for two-time division drive of the drive LSII, 1'.

When the signal electrode of the liquid crystal optical shutter 50 and the drive signal output of the drive LSII, 1' are connected in this way, the conductive patterns on the two circuit boards 62, 62' are left and right symmetrical, and each circuit board 62. It is necessary to mount a separate drive LS 11.1' on the chip 62', which has a symmetrical circuit configuration within the chip.

Therefore, in order to manufacture the optical recording head 60, two types of drive Sll and 1' are required, resulting in an increase in cost.

Therefore, the applicant of the present application previously filed an application for a recording device that solved this problem as U.S. Pat. No. 59-128611. The optical recording head 80 of the recording apparatus has a liquid crystal optical shutter 8 provided inside a head case 81, as shown in FIG.
Drive circuit boards 83, 83 are provided on both sides of vi 2, and the drive circuit boards vi 83, 83 are provided with the same drive L.
The signal electrodes of one drive LS 184 and the liquid crystal light shutter 82 are directly connected by a flexible connection member 85, and the signal electrodes of the other drive LSI 84 and the liquid crystal light shank 82 are connected by a flexible connection. It has a structure in which the member 86 is inverted and connected. Furthermore, since the two circuit boards do not need to have symmetrical circuits and can use the same circuit board (in other words, only one type of driving LSI is required), it is possible to use a common circuit board and reduce costs. It has this effect.

However, in the above-mentioned recording device, the circuit board and drive L
Although there is an advantage of having a common SI, it is necessary to connect one drive circuit board and the liquid crystal light shutter by inverting the flexible connecting member, which makes the connection process using thermocompression bonding complicated, and requires skill in the connection process. However, there was a drawback that the yield was poor.

Furthermore, since the connection is made inverted, the flexible member tends to peel off easily and lacks durability.

Therefore, the present applicant filed Japanese Patent Application No. 61-025064 in order to be able to construct an optical recording head using the same driving LSI chip without reversing the flexible member. In the print head of this recording device, an LSI package with a symmetrical circuit is manufactured by mounting the same driving LSI chip on the LSI package in the opposite direction, and this LSI package is formed with a symmetrical conductive pattern. The drive circuits are mounted on a drive circuit board having a drive circuit board, and drive circuits that are symmetrical to each other are configured. According to this method, only one type of drive LSI chip is required to be manufactured, but a pair of drive LS chips is
oard) or FPC (Flexible Pr
It is impossible to directly mount it on a 1inted C1rcuit Board, and there is a problem in high-density mounting.

For this reason, the present applicant has proposed a low-cost recording device incorporating a high-density packaging drive circuit that uses only one type of drive LSI and can be mounted as a pair of chips in Japanese Patent Application No. 62-123147. The application was filed as However, in this recording device, when the drive LSIs are connected in cascade, the input/output signal lines for the record data connected to each drive LSI cross each other, which makes the wiring pattern of the circuit board complicated, which poses a problem. 62-12314
(See Figures 4 and 8 of No. 7).

[Purpose of the invention]

In view of the above-mentioned conventional problems, the present invention incorporates a drive circuit in which one type of drive LSI that can be mounted at high density is mounted on a type of circuit board whose wiring pattern can be easily patterned, thereby achieving high productivity. The purpose is to provide a low-cost recording device.

(Summary of the Invention) In order to achieve the above object, the present invention has a plurality of recording elements arranged in a row for forming recording pixels on a recorded object, and has a plurality of recording elements arranged in a row on both sides of the recording element row. In a recording apparatus in which a plurality of drive means for supplying drive signals to recording elements are connected in cascade, the drive means is a shift register that stores a serially input recording signal and outputs the stored recording signal in parallel. an output means for outputting the drive signal based on the record signal outputted in parallel from the shift register; and a first switching means for switching the storage order of the record signals in the shift register in accordance with a switching signal; a second switching means for switching the cascade-connected input/output terminals according to the switching signal, and supplying mutually different switching signals to the driving means disposed on each side of the recording element to control the driving means. It is characterized in that the same driving means is used on both sides of the recording element by making the order of the cascade connection of the recording elements opposite to each other on each side.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

First, FIG. 10 is a schematic configuration diagram of a recording apparatus 100 according to this embodiment, and the configuration of the recording apparatus 100 will be explained according to FIG. 10.

In the figure, a photosensitive drum 101 is constructed by coating or vapor depositing a photoconductive fluorescent substance on the outer peripheral surface of a cylindrical tube made of metal such as aluminum, and rotates in the direction of the arrow B in the figure during recording operation. . A charger 102, an optical recording head 103, a developer 104, a transfer device 105, a cleaner 106, and the like are arranged around the photoreceptor drum 101.

The charger 102 performs corona discharge on the surface of the rotating photoreceptor drum 101 to charge the surface of the photoreceptor drum 101 to a predetermined potential, and the optical recording head 103 charges the photoreceptor drum 101 to a predetermined potential. 101 is irradiated with light according to the image to be recorded to form an electrostatic latent image (
Details of the optical recording head 103 will be described later).

The electrostatic latent image formed on the surface of the photosensitive drum 101 is developed into a toner image by a developing device 104 containing toner.

This toner image overlaps with the transfer paper 107 that is conveyed in synchronization with the toner image by a conveyance means (not shown), and the transfer device 1
The image is transferred onto the transfer paper 107 by the corona discharge of 05.

The toner image transferred onto the transfer paper 107 is fixed onto the transfer paper by a fixing device (not shown), and the transfer paper 107 with the toner image fixed thereon is discharged outside the machine.

Further, toner remaining on the surface of the photoreceptor drum JA101 without being transferred to the transfer paper 107 during transfer is removed by a cleaner 106.
is removed from the surface of the photoreceptor drum 101.

Next, FIG. 11 is a sectional view of the optical recording head 103. The configuration of the optical recording head 103 will be described below with reference to the same figure.

A liquid crystal optical shutter 111 is provided within the optical recording head 103. FIG. 12 is a perspective view showing the structure of the liquid crystal light shutter 111. As shown in the figure, the liquid crystal light shutter 111 is constructed by sealing a liquid crystal agent (not shown) between a lower glass substrate 131 and an upper glass substrate 132. A signal electrode 133 is formed on the upper surface of the lower glass substrate 131,
Two common electrodes (not shown) extending in a direction substantially perpendicular to the signal electrode 133 are formed on the lower surface of the upper glass substrate 132, and a micro-shutter 134 is formed at the intersection of the signal electrode 133 and the common electrode. There is.

Each micro-shutter 134 supplies a predetermined drive signal to a common electrode, and each signal electrode 133 supplies a predetermined drive signal to a common electrode.
4 are individually opened and closed by supplying an opening/closing drive signal for opening and closing them.

Next, returning to FIG. 11 again for explanation, a fluorescent lamp 11 which is a light source for irradiating light to the liquid crystal light shutter 111
2 is housed in a lamp case 113, and the space within the lamp case 113 is configured to allow air to circulate in order to cool the fluorescent lamp 112. LCD light shutter 1
11 is a head base 11 for accurate positioning.
4, and the imaging lens array 115 is also fixed at a predetermined position on the head base 114 in order to determine its positional relationship with the liquid crystal light shutter 111.

A drive circuit board 116 is provided on both sides of the lamp case 113, and on the drive circuit board 116 is mounted a paired chip drive LS 1117 in which a driving circuit is formed into an LSI. Furthermore, the drive circuit board 116 has the above-mentioned drive LS 111 at the lower end of the surface facing the lamp case 113.
Conductive patterns (not shown) drawn out from 7 are formed at a pitch equal to the pitch at which the signal electrodes 113 are arranged.

The conductive pattern of the drive circuit board 116 and the signal electrode 133 of the liquid crystal light shutter 111 are connected by a film-like electrode connector 118, which is a flexible connector having a connection pattern formed at a pitch equal to the pitch described above. .

A drive circuit board 119 for supplying a common electrode drive signal is provided above the lamp case 113, and the drive circuit board 119 contains a 20-odd volt signal that actually applies a logic level signal waveform to the common electrode. A high-voltage Drino<120 for waveform replacement is mounted, and the drive circuit board 119 and the common electrode are connected by a connector (not shown).

FIG. 13 is a partially enlarged view of the liquid crystal light shutter 211.

The signal electrode 133 is composed of a transparent conductive part 133a made of tin oxide, indium oxide, etc. and a metal electrode 133b of chromium, gold, etc., and the common electrode 135 is similarly composed of a transparent conductive part 135a and a metal electrode 135b. A micro-shutter 134 is formed in a portion where the transparent conductive parts 133a and 1353 face each other, and the micro-shutter 134 is opened and closed by a signal applied to the picture electrode.

Since each signal electrode 133 faces two common electrodes 135, two micro shutters 1 are provided on each signal electrode 133.
34 is formed. This is because two-time division driving is performed in order to reduce the number of drivers for opening and closing each micro-shutter 134.

Next, FIG. 14 is a block diagram showing a circuit configuration of a recording control section 140 which includes a liquid crystal optical shutter 111 and a driving LS 1117, 117' in the optical recording head 103.

In the figure, 134-1.134-2 is the same micro shutter as the micro shutter 134, and 135-1
．． 135-2 is the same common electrode as the common electrode 135. As shown in the figure, the LC3 drive signals PTI, PT2, and timing signal DS open and close the micro shutter.
EL and CK2 are connected to the drive LS111 via the control bus CB.
7. Enter 117'. Also, Microsha 2ri1
LC3 drive signals COMI and C0M2, which select which of 34-1. and is applied to the common electrodes 135-1 and 135-2. Clock signals CKIA and CKIB are alternately driven by two pulses each from the video interface section (described later) to the LS111? , 117゛, this CKI
The recording data LTXD is taken into the drive LS 1117' or 117 in synchronization with A or GKIB.

Here, the circuit configuration of the video interface section 150 is shown in FIG. As shown in the figure, the video interface section 150 receives recording data HLTXD in synchronization with a clock signal (LTXCK) from a printer controller (not shown), and receives recording data HLTXD from a printer controller (not shown).
Divide the frequency of TXCK and generate two pulses alternately 2
Two pulse signals CKIA and CKIB are generated and output to the drive LS 1117 and 117' together with the recording data LTXD. Note that the pulse signals CKIA and CKIB are generated only while HTWSX input from the LC3 drive circuit (not shown) is at L level. Therefore, the recording data LTXD (first 1
Assume that serial numbers are assigned in order from number 1 from the bit data) are (1, 2), (5, 6
), (9, 10), ... bit data are sent to the upper LSC drive LS1117'' (3, 4), (7, 8),
(11, 12)... LC whose bit data is in the lower row
Input to 3 drive LS1117.

Next, FIG. 1 shows the drive LS according to the first embodiment of the present invention.
1160 (in FIGS. 12 and 14, the drive LS 1117.
Although shown as 117', since these are the same LSI, they are driven in this figure and are collectively referred to as 31160. ) is a block diagram showing the circuit configuration of. In the same figure, ζ [
Problems with Prior Art], the same symbols are used for the same circuits as the drive LSII shown in FIG. 17 described above, and detailed explanations will be omitted. Next, a circuit configuration different from that of the driving LSII will be briefly described.

In the driving LS 1160 of the present invention, a data selector 171 is inserted before the shift register 11 in the circuit 170 of each channel. The circuit configuration of 171 is shown in FIG. Hereinafter, the circuit 170 that outputs channels Y1 to YH6 will be referred to as channels Y1 to Y06.

The gate terminal G1 of the data selector 171 has an external terminal R.
The input of EV is input through the inverter 172, and the input of the external terminal REV is input to the gate terminal G2.
, are input via the inverter 173. As can be seen from the circuit configuration of FIG. 2, the data selector 171 selects the A input when the REV input is at L level, and selects the B input when it is at H level.

Furthermore, in this embodiment, since the data delay is not controlled by the delay part 13 in the circuit 170, the terminal T2 is not provided, and the output of the Nandt gate 25 of the latch pulse generator 20 is supplied to the delay part 13 through the inverters 181 and 182. Part 13
Enter the clock terminal stone. Furthermore, a clocked inverter 18 is provided after the cascade output buffer 183.
3b is used. The clocked inverter 183b receives an inverted input G+ (REV) of the external terminal REV inputted through the inverter 172, and when G is at the low level, the clocked inverter 183b becomes high.
Therefore, the recording data input from the data terminal Dt becomes the B input of the data selector 171 of channel Y via the cascade output buffer 184.

Furthermore, the output of the shift register 11 of channel Y becomes the B input of the data selector 171 of channel Y2, and the output of the shift register 11 of channel Y2 becomes the B input of the data selector 171 of channel Y2.
The output of the channel (Y, 1+,) becomes the B input of the data selector 11 of channel Yl, such that the output of channel (Y, 1+,) becomes the B input of the data selector 11 of channel Yl. Further, the output of the shift register 11 of the channel Y□ is input to the cascade output buffer 185, and the output of the cascade output buffer 185 is sent to the channel Y□ via the cascade output buffer 186 which is also used in the driving LSII.

It becomes the A input of the data selector 171 and the terminal D+
It is connected to the. The downstream buffer of the cascade output buffer 185 is a clocked inverter 185b, and the clock signal of the clocked inverter 185b includes a signal from an external terminal REV.
The signal G2 is inputted via the signal G2.

Therefore, when REV is at L level, clocked inverter 185b becomes high impedance, clocked inverter 183b becomes a normal inverter, and circuit 17
Since the data selector 171 in 0 selects the A input, the recording data input from the data terminal D1 is channel Y.
gs,→Y! 55→Y□4→・・・→・・・Y2→Y
, and then the cascade output buffer 18
3, the signal is output from the data terminal Dt to the next stage drive 31160 (not shown).

- On the other hand, when REV is at H level, the cloth inverter 183b becomes high impedance, the clocked inverter 185b becomes a normal inverter, and the data selector 171 of the circuit 170 selects the B input, so that the recording input from the data terminal D2 Data is channel Y, →Y
2 - → Yzss - Y
160.

In this way, if the external terminal REV is set to L level, the drive L
S1160 is the data terminal D1 like the conventional drive LSI.
The recording data is input from the data terminal D2, and the recording data is shifted and output from the data terminal D2 to the driving LS 1160 at the next stage. on the other hand,
When the external terminal REV is set to H level, recording data is input from the data terminal D2, and the recording data is shifted and output from the data terminal to the next stage driving LS 1160.

Therefore, when connecting the drive LS1160 in cascade,
When REV is set to L level, the data input terminal becomes DI and the data output terminal becomes Dt. Also, when REV is set to H level, the data input/output terminals are reversed and the data input terminal is D2.
, the data output terminal becomes.

FIG. 3 shows the driving LS 1160 when driving the liquid crystal optical shutter 111 for two-time division driving using the driving LS 1160.
FIG. 2 is a schematic diagram showing a method of connecting the liquid crystal optical shutter 111 and the liquid crystal optical shutter 111. FIG.

In the figure, the liquid crystal light shutter 111 is a.

It consists of a plurality of micro shutters 134-1 and 134-2 arranged in a staggered manner at predetermined intervals in three rows, and the common electrode 13 of the 33 rows of micro shutters 134-1
The drive signal COM 1 is applied to 5-1, and the drive signal C is applied to the common electrode 135-2 of the micro shutter 134-2 in column b.
0M2 is input. Furthermore, driving LS 1160 is provided on both sides of the liquid crystal light shutter 111.
The 256 channel output of Il60 is liquid crystal optical shutter 1
It is connected to the signal electrode 133 of each of the eleven micro shutters 134-1 and 134-2. Micro shutter 13
4-1.134-2 has a common signal electrode 133, so two drive LSIs 160 arranged on both sides of the liquid crystal light shutter 134 can operate 1024 micro shutters 13.
4-1.Drives 134-2. In this figure, the inside of the driving LSI 160 is shown in a simplified manner, and the circuit 170 is shown only by the shift register 11 and the delay part 14. Furthermore, serial numbers from 1 to 1024 are attached to the recording data in the order of input bit data, and the serial numbers of the bit data stored in each shift register 11 are written.

The upper drive LS1160 sets the external terminal REV to Vss (L
level), the recording data LTXD is input from the data terminal D1. On the other hand, the lower drive LS11
Since the external terminal REV is set to VDD (H level), the recording data LTXD is input from the data terminal D2. Therefore, the video interface section 150
Of the recording data LTXD output from the upper drive L
Serial number input to S1160 (1°2)
, (5,6), (9,lO),... (1017,1
018), (1021, 1022) recording data LTX
D is stored in order from the shift register 11 on the data terminal D2 side in the form shown in FIG. In addition, the lower drive L
The recording data LTXD input to S1160 is sequentially (4, 3), (
8゜7), ... (1020,1019), (10
24, 1023) bit data of the serial number is stored. Record data LTXD from data terminal D2
Also in the shift register 11 of the lower drive LS 1160 to which
is stored in a shift register that is not connected to the

Next, the main operations of the recording apparatus 100 in which the drive LS 1160 is incorporated into the optical recording head 103 will be explained with reference to timing charts shown in FIGS. 4 to 6.

First, the recording device 10G performs recording for -line in synchronization with the fall of the write synchronization signal shown in FIG. 4 (al).

The drive LS 1160 shown in FIG. 1 can drive liquid crystal optical shutters with a 2.5-line delay arrangement and a 1.5-line delay arrangement, and by fixing T to the L level, the drive LS 1160 can drive a 2.5-line delay arrangement and a 1.5-line delay arrangement. By fixing T to the H level, it is possible to drive a liquid crystal light shutter having a 1.5 line delay arrangement. Here, first, T1 is fixed at L level and 2
．． The case of driving a liquid crystal optical shutter with a 5-line delay arrangement will be described. When T is fixed at the level, the delay part 14 transfers the latched data to the delay part 13 in synchronization with the falling pulse of the clock pulse CK23.
Output to.

As described above, while the transfer permission signal HTWSX shown in FIG. 4(C) is at L level, the video interface unit 150 receives one line of data from the printer controller (FIG. 4(f)).
The recording data HLTXD shown in FIG.
Terminal D1 of 160 and terminal D of lower drive LS1160
Output to 2. This recording data LTXD is taken into the shift register 11 via the cascade output cover couch 186 of the upper drive LS 1160 (see FIG. 3) and the data selector 171 in synchronization with the falling edge of CKIA.
The lower drive LS116 synchronizes with the falling edge of CKIB.
The data is taken into the shift register 11 via the 0 cascade output cover sofa 184 and the data selector 171.

In addition, in FIG. 4, the clock pulse CK1 shown in (el)
indicates the AND of CKIA and GKIB.

When the transfer of one line of video data LTXD is completed, HTWSX goes to the H level, and after a predetermined period of time, four pulses following the latch pulse CK2 shown in FIG. 3(b) are generated.

When this latch pulse CK2 is generated, the data select signal DSEL shown in FIG.
From 2.23, pulse CK21 whose phase is sequentially shifted,
CK22 and CK23 are output. This pulse CK21
, CK22, and CK23, the even-numbered bits of the recording data LTXD stored in the delay section 13 are latched by the data latch section 12, and the recording data is delayed by one line from the recording data LTXD stored in the delay section 14. Even numbered bits of the recording data LTXD, which is delayed by two lines and which has been taken into the shift register 11, are taken into the delay part 14.
be taken in.

Further, the odd bits of the recording data LTXD that have been loaded into the shift register 11 are loaded into the data latch section 15 by the pulse CK21.

The data selector modulator 16 receives a micro-shutter closing signal P having a cycle of T and /2 as shown in FIGS. 6(d) and (e).
TI, open signal PT2, and period T shown in FIG. 6(a).

A data select signal DSEL and its inverted signal DSEL, which are at L level in the first half and H level in the second half, are input. Also, the period T is determined by the data select signal DSEL.

The A input of the data select modulation section 16 (odd bits of recording data LTXD) is input in the first half of the process, and the B input of the data select modulation section 16 (even bits of recording data LTXD) is input in the second half of the data select modulation section 16.
is selected, and depending on the value of the selected bit data, the close signal PTI or the open signal PT2 is sent to the level shifters ll, -.
The signal is applied to the signal electrode 133 via the inverter 18 and the high pressure output buffer 19. Also, Fig. 6(b) and (C)
The drive signals COMI and C0M2 shown in are high voltage.
The common electrode 13 is level-shifted by the driver 120.
5-1.135-2, the micro shutter 134-1 formed on the common electrode 135-1 in the first half of period T, 4 is applied to the common electrode 135-2 in the second half of period T-.
A micro shutter 134-2 formed above is controlled to open and close based on recording data LTXD.

Therefore, odd bit pixels are recorded in the first half (T, /2) of the period T8, and even bit pixels are recorded in the second half of the period TH. The even numbered bits of the recording data LTXD are delayed by two lines with respect to the odd numbered bits by the delay part 13.
2), the recording is delayed by a total of 2.5 lines with respect to the odd bits, but during this 2.5 line delay, the photoreceptor 101 moves in the sub-scanning direction A shown in FIG.
Since the distance from microshutter 134-1 to microshafter 134-2 is then moved, recording is performed correctly.

On the other hand, when controlling a liquid crystal optical shutter with a 1.5 line delay arrangement, the external control signal T is set to H level.
The terminal stone of the delay part 14 is fixed at L level irrespective of the clock pulse CK23, so that even-numbered bit data stored in the shift register 11 passes through the delay part 14.

Therefore, even-numbered bit data stored in the shift register 11 in synchronization with the falling edge of the latch pulse CK22 is latched into the delay part 13 without being delayed by the delay part 14. Therefore, the even number bit data is 1 by the delay part 13 compared to the odd number bit data.
The data is latched into the data latch section 12 with only a line delay.

Therefore, data of 0 and even bits is recorded on the photoreceptor 101 with a delay of 1.5 lines relative to data of odd bits, but in a liquid crystal optical shutter with a 1.5 line delay arrangement, the micro shutter 134-1 shutter 134
-2, the photoreceptor 101 is 1.5 lines (1,
5T, ), and correct recording is performed.

Next, FIG. 7 shows a driving LSI which is a second embodiment of the present invention.
200 is a block diagram showing the circuit configuration of the 200. FIG.

In the figure, circuits common to the driving LS 1160 are indicated by the same symbols and detailed explanations are omitted.

The difference between the drive LSI 200 and the drive LS 1160 is as follows.
This is because the circuit configuration of the latch pulse generator 20 has been changed. That is, the latch pulse generating section 2 of the driving LSI 200
10, the X output (X2
1) becomes the l input of the flip-flop 22, and is also input to the Nant gate 213 via the Nant gate 211 and inverter 212. Also, flip-flop 2
The X output (X22) of 2 becomes the l input of the free-knob flop 23 and the flip-flop 216, and also becomes the input of the Nant gate 215 via the Nant gate 213 and inverter 214.

Furthermore, the X output (X23) of the flip-flop 23 is input to the Nant gate 215. Furthermore, an inverted signal (DSEL) of the external signal DSEL and an inverted signal of the external clock signal CK2 are input to the Nant gates 211, 213, and 215. Also, flip-flop 21.22
．． 23 operates in synchronization with the falling edge of the external clock signal CK2, but the flip-flop 216 operates in synchronization with the falling edge of the external clock signal CK2.
It operates in synchronization with the rising edge of L. In this way, the latch pulse generator 210 receives the external signal T like the latch pulse generator 20 of the drive LS 1160.

is not input, and the delay control of the delay portion 14 is performed using the X output (X3) of the flip-flop 216, as will be described later.

The operation of the latch pulse unit 210, which is the main part of the invention of the drive LSI 200 configured as described above, is illustrated in FIGS. 8(a) and 8(a).
This will be explained with reference to the timing chart of b).

First, FIG. 8(a) is a timing chart when controlling a liquid crystal optical shutter with a 2.5-line delay arrangement, in which the final pulse is generated in the clock signal CKI, and the circuit 1
After a time T1 after all the recording data for one line is stored in the shift register 11 of 70, the clock signal CK
2, five consecutive falling pulses are generated. As mentioned above, DSEL is at the H level in the second half of the period T and 11, and is at the L level in the first half, but as shown in FIG. Edges occur. When DSEL is at H level, one input of flip-flop 21 becomes H level, and the X output (X21) of flip-flop 21 changes from L level to H level in synchronization with the first rise of clock signal CK2.

Also, in synchronization with the rise of this clock signal CK2,
The X output (X21) of the flip-flop 21 is sequentially shifted to the l input of the flip-flop 22, and the X output (X22) of the flip-flop 22 is sequentially shifted to the l input of the flip-flop 23. Since the data being displayed is at L level, X22 and X23 remain at L level.

Next, when the clock signal CK2 rises, the X output (X21) of the flip-flop 21 is shifted to the flip-flop 22.
2) becomes H level. Also, at this time, since DSEL remains at H level, the X output of flip-flop 21 (X21
) is maintained at H level.

Next, when the clock signal CK2 rises, the DSEL
is at L level, so the X output of flip-flop 21 (X2
1) becomes L level and the data (X22) of the flip-flop 22 is shifted to the flip-flop 23, so
The X output (X23) of the flip-flop 23 becomes H level. Furthermore, since the data (X21) stored in the flip-flop 21 is input to the flip-flop 22, the H level is held. As described above, the data (X21) of the flip-flop 21 is shifted to the flip-flop 22, and the data (X22) of the flip-flop 22 is shifted to the flip-flop 23 in sequence in synchronization with the rise of the clock signal CK2. As shown in the timing chart of FIG. 8(a),
are pulses of period T whose rising edges are shifted by time T2. In addition, the flip-flop 216 is connected to the flip-flop 2 in synchronization with the falling edge of DSEL.
2's X output (X22) is taken in, and when DSEL falls, the flip-flop 22's X output (X22) is taken in.
Since is at the H level, X, after reaching the H level for -1 time, is continuously held at the H level. In addition, the output (T7) of the Nant gate 211 becomes L level only when DSEL and CK2 are L level and X21 is H level, so it falls to L level at the same time as DSEL falls to L level, and the next It rises to H level in synchronization with the rise of CK2. In synchronization with the falling edge of T', the even-numbered bits of data stored in the delay section 13 are latched into the data latch section 12, and at the same time, the odd-numbered bits of data stored in the shift register 11 are latched into the data latch section. 15. Next, when CK2 falls to L level again, DSEL and X21 become L level and X22
is at H level, so the output Cav of Nantes gate 213
) goes to L level and remains at L level until CK2 rises to H level. The data in the delay part 14 is latched into the delay part 13 in synchronization with the falling edge of 77.

Next, when CK2 falls to L level, DSEL,
Since X22 becomes L level and X23 becomes H level, the output (Tπ) of the Nant gate 215 falls to L level and is held at L level until the next rise of CK2. Engineering pi
When X3 falls, since X3 is at H level, a pulse ez having the same waveform as Tπ is added to the delay part 14, and the shift register 1
The even bit data stored as 1 is latched in the delay part 14.

As explained above, the clock signal CK2 is
) By creating a waveform with two rising edges while SEL is at H level, the drive LS
I200 can drive a liquid crystal optical shutter with a 2.5 line delay arrangement.

Next, FIG. 8(b) shows a timing chart when the driving LSI 200 drives a liquid crystal optical shutter with a 1.5 line delay arrangement.

In the case of controlling a liquid crystal optical shutter with a 1.5 line delay arrangement, the clock signal CK2 has a waveform with one rising edge when DSEL is at H level and three rising edges when DSEL is at L level.

As mentioned above, the flip-flop 21 latches DSEL at the rising edge of the clock signal CK2, so the X output (X21) of the flip-flop 21 rises to H level at the first rising edge of the clock signal CK2.
At the next rise, it falls to L level. In addition, the flip-flop 22 latches the X output (X21) of the flip-flop 21 at the rising edge of the clock signal CK2, but the waveform at that time is a rising pulse after DSEL becomes L level, as shown in the top of Figure 8. This is the waveform that is generated. Since the flip-flop 216 latches the X output (X22) of the flip-flop 22 at the falling edge of DSEL, the X output (x3) of the flip-flop 216 is held at the L level for -period Tw. Therefore, the clock signal T" input to the delay part 14 remains at the L level for one period T1 regardless of the output (■π) of the Nantes gate 215. The recorded bit data is transferred to the delay part 13 without being delayed by one line by the delay part 14.
It is latched at the falling edge of the clock signal T.

Therefore, even-numbered bits of recording data LTXD are recorded on the photoreceptor 101 with a delay of 1.5 lines relative to odd-numbered bits of recording data LTXD.

The driving LSI 200 is 1.5 as well as the driving LS1160.
Although it is possible to control liquid crystal optical shutters with a line delay arrangement and a 2.5 line delay arrangement, in order to generate the delay selection signal The signal T is not required, and the number of input pins is reduced by one. The drive LSI is a multi-pin LSI, and by reducing the number of input pins even by one, it is possible to reduce costs, which has a large effect.

Liquid crystal optical shutter 1 for driving LSI 200 in two time divisions
The method of connecting to the drive LS 1160 is the same as that of the drive LS 1160, and the configuration is as shown in FIG. 3 described above.

Next, FIG. 9 shows a schematic diagram of wiring connections when the driving LSI 200 of the present invention is cascaded to drive the liquid crystal optical shutter 134. The figure shows 40 per line.
This is a specific example in which four 256-channel drive LSIs 200 are cascade-connected on each side of a liquid crystal shank 111 that records 96 pixels, and the liquid crystal optical shutter 111 is driven. In the case of the drive LS 1160, the connection configuration is almost the same except that the number of external terminals T+ is increased by one.

As shown in the figure, in the cascade connection of the drive LSI 200, the upper drive LSI 200 is connected to an L level RE.
V is supplied to the lower drive LSI 200, and the RE of H level is supplied.
V is supplied to the data terminal D of the adjacent driving LSI 200.
Terminals D1 and D of the drive LSI 200 can be connected simply by connecting + and D2. By providing these at the rightmost and leftmost ends of the chip, respectively, cascade connection wiring becomes extremely simple.

Therefore, the wiring pattern of the circuit board becomes easier and the yield is improved. Furthermore, the bare chip driving LSI 200 is
It is also possible to implement the AB method and drive the liquid crystal optical shutter 111 by directly bonding the TAB lead to the signal electrode. In this case, a buff cage is not required, resulting in reduction in weight and size, improved productivity, and lower cost. will be brought about. Further, as is clear from the figure, since the wiring patterns of the circuit boards (relay boards in the case of the TAB method) on both sides are the same, only one type of circuit board (relay board) is required to be manufactured. In addition, in the case of the drive 5L1160, the drive 5L
Like the I200, the drive circuit can be configured with one type of drive 5L1160 and one type of circuit board.

In the above embodiment, only the case of driving a liquid crystal light shutter of two time division drive is described, but it goes without saying that the present invention can also be applied to the case of driving a general liquid crystal light shutter of N time division drive. .

In this case, the shift register of each channel consists of N flip-flops, and the number of lines in the delay part is (N-
1) Become pieces.

Furthermore, it goes without saying that the present invention can be applied not only to liquid crystal optical shutters but also to other types of recording apparatuses in which drive circuits are arranged on both sides of a recording element array.

〔Effect of the invention〕

As described in detail above, according to the present invention, the direction of the cascade connection of the driving LSIs disposed on both sides of the recording element can be freely changed by an external switching signal, and the direction of the cascade connection can be changed in accordance with the change in the cascade connection. Since the storage order of bit data stored in the shift register of each channel of the driving LSI can be changed, the following effects can be obtained.

a. Since only one type of driving LSI and a single type of circuit board on which the driving LSI is mounted is required, costs are reduced.

b. Bare-chip drive LSIs can be mounted in high density using the TAB method, which allows for increased pin count and thinner design.
It is possible to make it smaller and thinner.

At the same time, for example, the signal electrode and drive L of the liquid crystal light shutter
Connection with SI becomes easier and manufacturing yield improves.

Even when packaging the C0 drive LSI, there is no need to invert the flexible member when connecting the drive circuit board and the liquid crystal optical shutter, which improves manufacturing yield.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the circuit configuration of the first embodiment of the present invention, Figure 2 is a diagram showing the circuit configuration of the data selector section of the first embodiment, and Figure 3 is the block diagram of the circuit configuration of the first embodiment of the present invention. Schematic diagrams showing the connection configuration between the first embodiment and the signal electrode of the liquid crystal light shutter, FIGS. 4(a) to (1), FIG. 5(al to (1), and FIG. 6(a) to (e) 8(a) is a timing chart for driving a two-time division liquid crystal optical shutter using the first embodiment, FIG. 7 is a diagram showing the circuit configuration of the second embodiment of the present invention, and FIG. 8(a) , (b) is a timing chart for driving a two-time division liquid crystal optical shutter using the second embodiment, and FIG. FIG. 10 is a diagram illustrating the connection configuration when driving the recording apparatus of this embodiment, and FIG.
12 is a perspective view of the liquid crystal optical shutter, FIG. 13 is a partially enlarged view of the liquid crystal optical shutter, and FIG. 14 is a block diagram of the recording control section of the optical recording head. Figures: Figure 15 is a circuit configuration diagram of the video interface section, Figure 16 is a block diagram showing the circuit configuration of a conventional drive LSI, and Figures 17 (a), (b), and (C) are respectively FIG. 17 is a diagram showing the circuit configuration of the data selector modulation section, data latch section, delay section, and shift register section of the drive LSI. FIG. 18 is a block diagram of the recording control section of the conventional optical recording head. , FIG. 20 is a sectional view of a conventional optical recording head. 11...Shift register, 13.14...Delay part, 12.15...Data launch section, 16...Data selector modulation section, 20.210...Latch pulse generation section, to 103 knee - Optical recording head, 160.180... Drive LSI, 170... Channel, 171... Data selector, 183.185... Cascade output cover sofa, 183
b, 185b...Clocked inverter, 211.213.215...Nant gate, 212.
214...Inverter, 216...Flip-flop. Patent Applicant: Casio Electronics Industries Co., Ltd. Same as above Casio Computer Co., Ltd. J Figure 2 (b) Figure 8 Figure 10 Figure 11 Figure 12 Figure 19 Figure 20 Procedure ii Regular form (method) % formula % 1. Indication of the case 1986 Patent side No. 255602 2. Invention title recording device 3. Person making the amendment Relationship with the case Patent applicant name Casio Electronic Industries Co., Ltd. Representative Tadao Kashio Name (144) Casio Kashi, Representative of Calculator Co., Ltd.
Tadao O 4, sub-agent Postal code 102 Address 6-1-18 Kojimachi, Chiyoda-ku, Tokyo 1988
June 28, 2019 (Shipping port)? ,? lIi Correct content l) In the 6th and 7th lines of page 43 of the book M, it is written that ``Figure 4 (a) ~ (i), Figure 5 (a) ~ (ri, Figure 6 (a)
) to (e), using the above first embodiment” is replaced with “
Figures 4, 5, and 6 (a) to Te) are shown in Figure 1 above.
``Using Examples''. that's all

Claims (1)

[Scope of Claims] A plurality of recording elements arranged in a row for forming recording pixels on a recording object, and drive means for supplying a drive signal to the recording elements on both sides of the recording element row. In the recording apparatus, each of which has a plurality of recording devices connected in cascade, the driving means includes a shift register that stores serially input recording signals and outputs the stored recording signals in parallel; output means for outputting the drive signal based on a recording signal; first switching means for switching the storage order of recording signals in the shift register according to a switching signal; and cascade-connected input/output according to the switching signal. a second switching means for switching the terminals, and supplying mutually different switching signals to the driving means disposed on each side of the recording element to change the order of cascade connection of the driving means on each side. A recording device characterized in that the same drive means are used on both sides of the recording device by being in opposite directions.