JPH0198007A - Power supply circuit - Google Patents

Abstract

PURPOSE:To ensure the quick follow-up of the output voltage to the fluctuation of the power supply voltage by securing the capacitive connection between the gate electrodes of an FET which drives a node point having the reference voltage and an output node point. CONSTITUTION:The reference voltage VREF of a node point 3 serving as the output of a voltage divider 1 rises up in response to the rise of the power supply voltage VDD. As a result, a p-type FET Q2 is turned on and the voltage V5 of a node point 5 rises up owing to the capacity C2 applied between node points 3 and 5. While an n-type EFT Q1 is turned off with the rise of the voltage VREF. In this case, the voltage V4 of a node point 4 quickly rises up by the current supplied from a resistance R3 and the capacity C1. A p-type FET Q4 and an n-type FET Q3 are turned off and on with the rise of the V5 and the V4 respectively. Then the output V0 follows up quickly to the rise of the voltage VDD. Furthermore the output V0 also follows up quickly to the fall of the point 3 in case of the drop of the VDD.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power supply circuit, and more particularly to a power supply circuit whose output voltage is a voltage obtained by dividing a power supply voltage.

[Conventional technology]

In recent years, power supply circuits whose output voltage is a voltage obtained by dividing a power supply voltage have come to be widely used in semiconductor integrated circuits. Below, a conventional example will be shown and its configuration and operation will be explained.

FIG. 3 is a circuit diagram of a conventionally used power supply circuit. In FIG. 3, voltage divider 1 and current amplifier 12 are connected to node 3.
The output voltage at the node 16 is controlled to be equal to the reference voltage.

In voltage divider 1, resistors R1 and R2 are connected to the power supply V. If the normal voltage of the power supply VDD is VDDO, the reference voltage VRI! obtained at node 3 is connected in series between D and ground.
F is VRεF'= (Rz / (R1+R2)) ・
Voo.

becomes.

In the current amplifier 12, a resistor R3 and an N-channel MOS transistor (hereinafter referred to as NMO3FET) Ql whose gate electrode and drain electrode are short-circuited are connected in series between the power supply VDD and the node 3. Voltage V at node 14
14, the threshold voltage of NMO3FET is VTN,
Further, assuming that the resistance value of the resistor R3 is sufficiently larger than the resistance values of the resistors R and R2, V 14 = V REF + V TN.

Os transistor between resistor R4 and P channel (hereinafter referred to as PM
Q2, which is referred to as O3FET, is also connected in the same manner in a complementary manner, and the voltage VI5 at node 15 has the threshold voltage of PMO3FET as VTP, and the resistance value of resistor R4 is the same as that of resistor R4.
Assuming that the resistance values of V 1 and R2 are sufficiently large, V 15 = V REP + V 7p.

Node 16 is the output node of the power supply circuit, and includes the source electrode of NMOSFETQt whose drain electrode is connected to the power supply VDD, and the PMOSFET Qt whose train electrode is connected to ground.
The source electrodes of FETQ4 are connected together.

Next, the operation of the circuit shown in FIG. 3 will be explained. When the voltage Vo at the node 16 becomes lower than the reference voltage VREF at the node 3, the gate electrode voltage becomes V RB , which is the value of the voltage V14 at the node 14.
Since it is p + V TN, it becomes on state and the power supply ■
Current is supplied from DD to the load via node 16, and node 1
Voltage of 6 ■. act to prevent the decline of At this time, PMO8FETQ4 has its gate electrode voltage at node 1
Since the value of the voltage V15 of 5 is VREF+V7p, it is in the off state.

On the other hand, when the voltage o at the node 16 becomes higher than VR2p, the gate electrode voltage V14 of the NMO3FETQ becomes V
Since pIBp + V TN, PMOS FET Q 4 is in the off state, and since the gate electrode voltage V15 is V REF + VTP, it is in the on state, and current flows from node 16 to ground. flowing,
It operates to prevent the voltage Vo at node 16 from rising.

Therefore, the power supply circuit shown in FIG. 3 creates a reference voltage λEP from the power supply VDD using resistors R1 and R2, and outputs a voltage equal to this as the output voltage λEP. The circuit operates as a power supply circuit that supplies current to the load.

[Problem that the invention seeks to solve]

In the conventional power supply circuit described above, the reference voltage VFLIJ of the node 3 set by the resistors R1 and R2 is
In order to avoid being affected by variations in the threshold voltage or current characteristics of T and PMO3FET, the resistance values of resistors R3 and R2 are set to be sufficiently large compared to the resistance values of resistors R and R2. There is. For this reason, as will be described below, there is a problem in that the speed at which the output voltage follows fluctuations in the power supply voltage VDD is slow.

For example, if the voltage of the power supply ■DD is V as shown in a of FIG.
When increasing from DDO to VDDI, the voltage Vu at node 3
Due to the rise in gp, NMOSFETQt is turned off. Then, the stray capacitance at node 14, which is composed of the gate electrode capacitance of NMOSFETQt, etc., is charged via the resistor R3 having a large resistance value, and the voltage fluctuation of the reference voltage F at node 3 is caused by its time constant. The follow-up of the voltage 14 at the node 14 with respect to the voltage 14 is delayed as shown in g in FIG.

The voltage V15 at the node 15 immediately follows the reference voltage RO at the node 3, as shown in h in FIG. 4, because the PMO3FET Q2 is turned on due to the rise in the voltage RO at the node 3.

Due to the increase in voltage V15 at node 15, PMO8FE T
Q 4 is turned off and the voltage V14 at node 14 rises, causing NMOSFET Q 3 to turn on and the voltage V at node 16 increases. will increase. However, since the rise of the voltage VI4 at the node 14 is delayed as described above, the voltage at the node 16 is .

The rise of the reference voltage VREF at the node 3 is also delayed as shown in i in FIG. 4, and the rise in the reference voltage VREF at node 3 is also shown in f in FIG.

Similarly, power ■. When the voltage at D decreases, the decrease in the voltage VREP at node 3 turns on the NMOS FETQl, and the voltage V14 at node 14 immediately follows the voltage VREP at node 3. Shigashi, PMO3FE
TQ2 is turned off and the stray capacitance at node 15 is discharged through resistor R4, so the voltage V15 at node 15
The rate of decline in the output voltage V (1 is the voltage V at node 15) is slow.
15 causes a delay in following the decrease in reference voltage VREF.

Therefore, the conventional power supply circuit has a problem in that the output voltage follows the fluctuations of the power supply voltage DD slowly.

For example, when this power supply circuit is used as part of a memory circuit, the power supply voltage of the memory circuit is input, 1/2 of that voltage is output, and this output voltage is used for determining the output voltage level of the memory cell. However, when there is a fluctuation in the power supply voltage of the memory circuit, if the output voltage of the power supply circuit follows slowly, it may cause an error in determining the output voltage level of the memory cell. There are problems.

An object of the present invention is to provide a power supply circuit in which the output voltage follows a change in the power supply voltage V□(+) at a high speed.

[Means for solving problems]

The power supply circuit of the present invention uses a voltage divider that divides a voltage used as a reference voltage from a DC power supply voltage and a field effect transistor, and is controlled to output the same voltage as the reference voltage and supply current to a load. a power supply circuit comprising a current amplifier having a reference voltage, gate electrodes of N-type and P-type field effect transistors each having a source electrode or a drain electrode connected to an output node of the current amplifier, and an internal node having the reference voltage; It is configured with a capacitor connected between the two.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the power supply circuit of the present invention.

In FIG. 1, voltage divider 1 and current amplifier 2 are connected at node 3. In FIG. In current amplifier 2, node 3 and node 4
A capacitor C1 connected between the reference voltage VB and a capacitor C2 connected between the nodes 3 and 5 are connected to the reference voltage VB.
Node 3 with 2p and N M OS driving node 6
FET Qs and P M OS FET
A capacitive coupling is formed between Q4 and the gate electrode of Q4.

The operation of the power supply circuit shown in FIG. 1 is based on the voltage VD of the power supply V00.
When DO is constant, the circuit is similar to the secondary power supply circuit shown in FIG.

The operation of the circuit will be described below when the power supply voltage VDDO fluctuates.

In FIG. 1, when the power supply voltage ■oDo increases from vooo to VDDI as shown in a in FIG. 2, the reference voltage VREF at node 3, which is the output of voltage divider 1, becomes Vpp ) )・VDDI and rises as shown in b in FIG. In the current amplifier 2, due to the increase in the reference voltage λEF at the node 3, P
Due to the ON state of MO3FETQ2 and the capacitive coupling by the capacitor C2 provided between nodes 3 and 5, the voltage V5 at node 5 becomes equal to the reference voltage V at node 3.
Following the rise in RBp, it rises as shown in d in FIG.

Furthermore, NMOS FET Q1 is turned off due to the rise in voltage VREF at node 3, but due to current supply from resistor R3 and capacitive coupling due to capacitor C provided between nodes 3 and 4. The voltage at node 4 is
4 rises as shown at C in FIG.

In the conventional power supply circuit shown in FIG. 3, the increase in voltage V14 at node 14 due to the increase in reference voltage VREF at node 3 was caused only by the charging current from resistor R3, whereas in the conventional power supply circuit shown in FIG. In the power supply circuit according to the invention, the rise in the reference voltage VREF at node 3 is transmitted to node 4 through capacitor C1, so that the reference voltage VRI! The voltage v4 at the node 4 quickly follows the rise in F.

Due to the increase in voltage V5 at node 5, PMO8FET Q
4 is in the off state, and due to the rise in voltage V4 at node 4,
Since NMOSFETQ3 is in the on state, the output voltage VO is equal to the power supply VD as shown in e of FIG.
This will quickly follow the voltage rise of D.

Similarly, when the voltage of the power supply VpO decreases, the reference voltage VR2p of the node 3 decreases, so that NMO8F ET
Due to Q1 being turned on and capacitive coupling by capacitor C1 provided between nodes 3 and 4,
Voltage 4 at node 4 quickly follows the drop in reference voltage VF at node 3. Voltage 5 at node 5 is not only due to discharge due to resistor R4 at node 5, 3 and node 5
A decrease in the reference voltage VREF at the node 3 is transmitted to the capacitor C2 provided between the two nodes, so that the reference voltage VREF quickly decreases.

Due to the drop in voltage V4 at node 4, NMOSFET Q
3 is in the off state, and due to the decrease in the voltage 5 at node 5,
Since PMOS FET Q4 is turned on, the output voltage Vo quickly follows the voltage drop of the power supply VDD.

〔Effect of the invention〕

As explained above, the present invention provides a capacitive coupling between a node having a reference voltage in a power supply circuit and the gate electrode of a field effect transistor that drives the output node, thereby reducing fluctuations in the power supply voltage. This has the effect that the output voltage can quickly follow.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of an embodiment of the present invention, Figure 2 is a waveform diagram showing voltage fluctuations at each node with respect to power supply voltage fluctuations in the circuit shown in Figure 1, and Figure 3 is a conventional power supply. The circuit diagram of the circuit, FIG. 4, is a waveform diagram showing voltage fluctuations at each node with respect to power supply voltage fluctuations of the circuit shown in FIG. 3. 1... Voltage divider, 2, 12... Current amplifier, 3° 4.5.6.14, 15.16... Node, Ql. Q3...NMOSFET, Q2, Q4...
...PM○5FET, R,, R2, R9, R4...
...Resistor, C1, C2...Capacitor. Agent Patent Attorney Otsuka Uchihara Part 2 vJ Figure 3 Part 4

Claims (1)

[Claims] A voltage divider that divides a voltage used as a reference voltage from a DC power supply voltage, and a current amplifier that uses a field effect transistor and is controlled to output the same voltage as the reference voltage and supply current to the load. In the power supply circuit, the capacitor is connected between the gate electrodes of N-type and P-type field effect transistors whose source electrodes and drain electrodes are respectively connected to the output node of the current amplifier and the internal node having the reference voltage. A power supply circuit characterized by comprising: