JPH0198189A - semiconductor memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory and a sense circuit for reading signals from the semiconductor memory, and is particularly applicable to high-speed, highly integrated DRAM and SR.
This invention relates to a high-speed, highly stable sense circuit suitable for AM.

[Conventional technology]

A conventional memory sense circuit generally has a configuration as shown in FIG. Also, the method to improve it is
IEE International Solid State Circuit Conference (1986) pp. 262-263 (IEE, I
international solid-3tat
e C1rcuits Conference 198
6.

PP, 262-263).

[Problem to be solved by the invention]

A conventional sense circuit has a configuration as shown in FIG. Note that although a sense circuit for a dynamic memory will be described here, a sense circuit can be similarly configured for a static memory by placing a memory cell of the static memory in place of the memory array and sense amplifier.

In the figure, 1 is a dynamic memory cell array, 2 is a CMO8 sense amplifier, 3 is a column switch, and 4 is an on-state of the gate of column switch 3.

5 is a decoder that selects an address; 6A and 6B are I10 lines that transmit signals;
input/output lines), 8 and 20 are load elements that give the potential of the I/O wires 6A and 6B, 9 and 10 are the load capacitances that are generated parasitically on the I10 lines 6A and 6B, 12 is the I/O line 6A, This is a voltage amplifier that amplifies the 6B signal voltage difference.

In the conventional sense circuit, the loads 20 and 8 are driven by a sense amplifier serving as a signal source, and the signal voltage difference between the I10 line pair 6A and 6B is amplified to a large voltage difference by the voltage amplifier 12. Information read by one sense amplifier was amplified and output.

FIG. 3 shows that in this conventional example, when the address is switched,
It shows the operation waveforms when reading different information continuously.

In the figure, τ1 is the time from when the address is switched until the signal voltage of the G/○ line crosses.

τ2 indicates the time from when the signal voltages of the 10 lines cross until the signal output is applied to the output of the amplifier 12.

In the conventional memory, since a method is used to amplify the voltage amplitude of the I10 line, it is necessary to make the voltage amplitude of the C/○ line large (>200 mV). For this reason, when reading different signals, the time τl required for the voltages of the wires to cross each other increases, leading to an increase in the time required to read information. To do.

The signal delay τ1 on the I10 line has been a major obstacle to realizing a high-speed memory LSI. For example, depending on the magnitude of the operating current, the value of τ1 is 70% of the value of 2 for the total delay τ□+.
%.

Furthermore, when reading a different signal, a signal voltage corresponding to the previous read information remains on the I10 line, which tends to cause malfunctions in which the sense amplifier information is inverted. Therefore, the ratio (gate width to gate length ratio) of the transistors in the column switch cannot be made larger than the ratio of the transistors in the sense amplifier, which is a major obstacle to increasing speed and operating margin of the circuit.

A means of increasing the operating speed of the I10 line sense circuit is discussed in the above-mentioned document, IEE International Solid State Circuit Conference (1986), pages 262-263. There is. In this example, a minute voltage change on the 1/○ line is amplified, but the voltage gain is as low as 35, so in order to obtain a voltage amplitude of 5V, I10
The line signal voltage requires a value of about 140 mV. Although this value is slightly lower than that of the conventional sense circuit described above, it is not much different, and it cannot be expected to significantly improve signal delay.

[Means to solve the problem]

In order to solve the above problems, the present invention provides a current-voltage converter that includes a mechanism for stabilizing the potential of the I10 wire that transmits signals, and a mechanism that converts the signal current flowing through the I10 wire into a signal voltage. The mechanism was used as a means of amplifying the signal.

[Effect]

The current-voltage conversion mechanism of the present invention operates to stabilize the potential of the ■/○ wires. As a result, the potential of the I10 line is
Regardless of the information, it is a constant value. Therefore, the delay until the voltages of the I10 lines cross when different information is read can be significantly shortened. Furthermore, since the potential difference between the I10 line pair is approximately Ov, the operational margin when reading different information can be improved.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings. In the following example, a sense circuit of a dynamic memory will be described, but a sense circuit of a static memory will also be described.
A sense circuit can be similarly configured by placing static memory memory cells in place of the memory array and sense amplifier.

FIG. 1 shows an embodiment of the invention. In Figure 1, 1
2 is a dynamic memory memory cell array, 2 is a sense amplifier that amplifies information read from the memory cells,
3 is a column switch for reading the information amplified by the sense amplifier to the I10 line (input/output line) and writing information to the memory cell from the ■/○ line; 5 is a column switch for selecting one of the multiple sense amplifiers. 4 is its output line, 6A and 6B are I10 lines (input/output lines) for transmitting signals, 9.10 is the parasitic capacitance of the I10 line, 8 is a write circuit,
11 is an I/V converter (current-voltage converter), 13.1
4 is an amplifier, 15.16 is a feedback circuit, 7A,
7B is the output of the I/V converter, 12 is the voltage amplifier, 1
7.18 respectively show differential amplifiers.

The operation of this embodiment will be explained below using this figure. Information read from the memory cells is amplified by the sense amplifier 2. Thereafter, the column switch 3 connects the sense amplifier 2 and the I10 line pair 6A, 6B. At this time, the sense amplifier 2 tries to pull down one of the I10 line pairs to the low voltage side according to the information read from the memory cell. In other words, this is equivalent to a state in which a signal current source is connected to one of the pair of wires. Next, the work/V converter 11 detects the signal current of the work/○ wire versus the earth, and outputs a voltage proportional to the signal current to 7A and 7B. At the same time I/V
The converter 11 connects the output side (7A, 7B) to the input side (
6A and 6B) through feedback circuits 15 and 16, I10
Stabilize the potential of wire pair 6A and 6B.

FIG. 4 shows waveforms of various parts during signal readout operation.

Since almost no potential difference appears on the I10 line, when reading different information, the time required for the potentials of the I10 line to cross can be made extremely small. The time τC until the output voltage of the I/V converter crosses is determined by
It is determined by the charging and discharging time in 3.14. Since the load capacitances of the output cuffs A and 7B are sufficiently smaller than the capacitance of the I10 line, the delay τC becomes an extremely small value. As a result, the total delay τ1+τC+τ2 can be significantly shortened compared to the conventional method.

Here, the I/V converter, which is the most distinctive feature of the present invention, will be explained in detail. The roles of the I/V converter, as stated above, are (1) to convert the signal current on the I10 line into a voltage, and (2) to stabilize the potential on the I10 line.

Examples of the I/V converter will be described below.

[Embodiment 1 of I/V Converter] FIG. 5 shows a first embodiment of the I/V converter. In the figure, 41A and 4 insulation are I/V converters connected to I10 lines 6A and 6B, respectively.

Each I/V converter includes N-channel intermediate S transistors 42 to 44 and P-channel MTS transistors 45 and 46.
, and a resistor 47. Transistors 42 to 46 input I10 line 6A and reference voltage VR, and 7
It constitutes a differential amplifier with A as an output. The differential amplifier corresponds to the amplifier (13, 14) in FIG. 1, and the resistor 47 corresponds to the feedback circuit (15, 16) in FIG.

The operation of this embodiment will be explained below. The output signal voltage VO of the I/V converter is expressed by the signal current 1+ of the I10 line as vo=Rc-i+. Here, Re is a resistance value of 47.

Therefore, by setting the value of Rc appropriately,
While keeping the potential of the line constant, the signal current i.

A signal voltage proportional to can be obtained at the output.

[Embodiment 2 of I/V Converter] FIG. 6 shows a second embodiment of the I/V converter. In the figure, 51A and 5 insulation are I/V converters connected to I10 lines 6A and 6B, respectively.

56 is a P-channel intermediate S transistor, 57 is a current source, and 56 and 57 constitute a bias circuit for an inverter included in the I/V converter. Each 1/V converter includes N-channel MIS transistors 52, 53,
It is composed of a P-channel intermediate S transistor 54 and a load 55. 52 and 54, I10 line 6A
Configure an inverter with 7A as input and 7A as output,
3.55 constitutes a voltage controlled current source driven by the output of the inverter. The inverter corresponds to the amplifier (13, 14) in FIG. 1, and the voltage controlled current source corresponds to the feedback circuit (15, 16) in FIG. 1, respectively.

The operation of this embodiment will be explained below. The inverter is biased so that a constant current flows. Therefore, if a potential Vcs of 50 is applied, the output cuff A is set so that the I10 line 6A (7) potential becomes Vcs+Vth (52).
The voltage of is determined. The output voltage V (7A) is V (7A) = Vcs + Vth (52) +Vth
(53). Here, vtl, (52), V
th (53) represent the threshold voltages of the N-channel M and IS transistors 52 and 53, respectively. Engineering／○
The signal voltage of the line is vl, the signal current of the I10 line is i4, I/
The output signal voltage of the V converter is V. Then vo=□・
i.

vl: "l+m-G" where g is the transfer conductance of the transistor 53, and G is the voltage increase +111 of the inverter.

As a result, the voltage amplitude of the I10 line is 1/G of the output voltage m width.
become. Therefore, the output voltage amplitude > 200 mV
For example, it is easily possible to set G to a value of about 50, and the voltage amplitude of the F0 line only needs to be about 4 mV.

With these, after stabilizing the potential of the I10 line,
A signal voltage proportional to the signal current of the 0 line can be obtained as an output.

[Embodiment 3 of I/V Converter] FIG. 7 shows a third embodiment of the I/V converter. In the figure, 61A and 6 insulation are I/V converters connected to I10 lines 6A and 6B, respectively.

Each I/V converter includes an N-channel intermediate S transistor 62-65. P-channel MIS transistor 66.67
, and a load 68. Transistors 62, 63, 64, 66゜67 form a differential amplifier that takes I10 line 6A and reference voltage VR as input and outputs 7A, and 63 and f3B form a voltage driven by the output of the differential amplifier. It constitutes a controlled current source. The differential amplifier corresponds to the amplifier (13, 14) in FIG. 1, and the voltage controlled current source corresponds to the feedback circuit (15, 16) in FIG. 1, respectively.

Since a differential amplifier is used in this embodiment, the voltage of the power line 10 can be made equal to the reference voltage VR.

That is, it has a feature that the potential of the I10 line can be freely set by controlling the VR.

Furthermore, since the potential of the I10 line remains constant regardless of the value of the operating current of the differential amplifier, a circuit with a large operating margin can be provided.

[Embodiment 4 of I/V Converter] FIG. 8 shows a fourth embodiment of the I/V converter. In the figure, 70A and 70B are I/V converters connected to I10 lines 6A and 6B, respectively.

Each I/V converter includes N channel MIS transistors 71 to 73 and P channel MIS transistors 74 to 76.
, and a load 77. Transistors 71, 72, 73, 75゜76 constitute a differential amplifier that takes I10 line 6A and reference voltage VR as input and 7B as output, and 74.77 configures the voltage driven by the output of the differential amplifier. It constitutes a controlled current source. The differential amplifier corresponds to the amplifier (13, 14) in FIG. 1, and the voltage controlled current source corresponds to the feedback circuit (15, 16) in FIG. 1, respectively.

Unlike the previous embodiments, this embodiment uses a P-channel intermediate S transistor as a voltage-controlled current drive element, so it has a feature of good power usage efficiency.

That is, since the output voltage of the I/V converter is a voltage lower than the voltage VR of the I10 line, it is possible to set VR high to a value close to the power supply voltage Vcc.

In addition, all of the embodiments so far have used a 1-inverting type (input 6A and output cuff A have opposite phases) amplifier and a non-inverting type (input 6A and output cuff A) amplifier.
(The phase is not reversed between Hecuff A and output 6A) using a feedback circuit.

I was giving negative feedback. The feedback circuit of this embodiment is of an inverted type because it uses a P-channel interlayer S transistor. Therefore, the amplifier is of a non-inverting type.

[Embodiment 5 of I/V converter] In Fig. 9, which shows a fifth embodiment of the I/V converter, 70A and 70B are I/V converters connected to I10 lines 6A and 6B, respectively. .

The difference from the previous embodiment is that an N-channel intermediate S transistor 78 is added. In the previous embodiment, since the wire/○ wire is connected to the drain of the P-channel MIS transistor 74, the impedance is high and the response when a signal current flows transiently is somewhat difficult. In contrast, in this embodiment, a diode-connected N-channel MIS transistor 78 is added in parallel with the P-channel intermediate S transistor 74 to lower the impedance of the I10 line and improve transient response. In addition, since the voltage of the I10 line becomes Vcc Vth (Vth is the threshold voltage of the N-channel MIS transistor), the voltage of the I10 line becomes Vcc by the N-channel MIS transistor 79.
A voltage Vth is generated and used as a reference voltage VR.

Next, the data write operation will be explained. FIG. 10 shows an embodiment of the write circuit (8 in FIG. 1), and FIG. 11 shows waveforms of various parts during write operation. In the figure, Di and l are data input terminals, 80 is a data manual buffer, 81.82 is an inverter, 83.84 is an N-channel intermediate S transistor, and I10 line 6A.

Connected to 6B. Data input from the Dll is latched by a data manual buffer.

While the write timing signal φ is at a low potential, it is in a read state, so the voltage stabilization mechanism of the I/V converter described above works, and the I10 lines 6A and 6B are at almost the same potential. φ, becomes a high potential, and the transistor 83.
When 84 becomes conductive, true and complementary signals of input data are written into 6A and 6B, respectively. i.e. according to the input data.

One of 6A, 6B has a high potential and the other has a low potential. This data is written into the selected memory cell through column switch 5 and the data line.

When φ becomes a low potential, 6A and 6B return to almost the same potential.

Note that it is desirable from the viewpoint of power consumption to stop the operation of the I/V converter during the write operation. To do this, for example, the signal with the opposite phase of the write signal φ1 may be set to φE in FIG. 5 (or FIGS. 7, 8, and 9).

In the above embodiment, a memory sense circuit using complementary MIS transistors has been described.

The present invention can be similarly applied as long as it includes means for stabilizing the voltage of the I10 line and means for outputting a voltage related to the signal current of the I/O line. For example, the sense circuit can be similarly configured using a single-polarity M/S transistor, a combination thereof, or other circuit systems.

In particular, memory arrays are MIS transistors.

By using bipolar transistors in the sense circuits of the engineering/○ lines, it is also possible to provide extremely high-speed, highly integrated memory LSIs that take advantage of the performance of the elements.

〔Effect of the invention〕

According to the present invention, it is possible to reduce the delay in the sense circuit section of a dynamic memory or a static memory, thereby making it possible to provide a faster semiconductor memory. Furthermore, since malfunctions can be prevented when different information is read, a highly reliable semiconductor memory can be provided.

[Brief explanation of the drawing]

FIG. 1 is a sense circuit diagram of an embodiment of the present invention, FIG. 2 is a conventional sense circuit diagram, FIG. 3 is a signal timing diagram showing the operation of the conventional sense circuit, and FIGS. 4 and 11 are according to the present invention. 5, 6, 7, 8, and 9 are diagrams showing the specific configuration of the I/V converter in the embodiment of the invention. , FIG. 10 is a diagram showing a concrete development diagram of a write circuit in an embodiment of the present invention. 5. Explanation of symbols 1...Dynamic memory cell array, 2...
Sense amplifier, 3... Column switch, 4... Address designation signal, 5... Address decoder, 6A, 6
B...I10 line, 8...Write circuit, 11...I
/V converter, 12...voltage amplifier. Figure 5, Figure 5, Figure 5' Biao Kahu: Tribute Chu, 7th θth, 9th month, 77th month, 7th month, 7th month, 7th month, 7th month, 7th month, 7th month, 7th month, 7th month, 7th month, 7th month, 7th month, 7th month.

Claims (1)

[Claims] 1. A memory cell array consisting of a plurality of memory cells;
Selects at least one data line to which a memory cell is connected and one memory cell from a plurality of memory cell arrays, and selects an address selection mechanism connected to the data line and a voltage of the address selection mechanism connected to the data line. A mechanism for amplifying according to information in memory cells, an input/output line connected to the data line via a column switch selected by a column address, and a main amplifier connected to the input/output line. A semiconductor memory sense circuit characterized by having a voltage stabilizing mechanism and an amplifying mechanism. 2. In the sense circuit according to claim 1,
A sense circuit for a semiconductor memory, characterized in that the voltage stabilizing mechanism includes at least a current-voltage converting mechanism that receives an input/output line as an input. 3. In the sense circuit according to claim 2,
The current-voltage converting mechanism includes a differential amplifier that receives the voltage of the input/output line as one input and a reference voltage source as the other input, and is controlled by the output of the differential amplifier and supplies current to the input/output line. 1. A sense circuit for a semiconductor memory, comprising at least a voltage-controlled current drive element. 4. In the sense circuit according to claim 3,
The voltage controlled current drive element is an insulated gate (MI
A semiconductor memory sense circuit characterized by using an S) type transistor. 5. In the sense circuit according to claim 3,
The current-voltage conversion mechanism includes at least an inverting amplifier (inverter) that inputs the voltage of the input/output line, and a voltage-controlled current drive element that is controlled by the output of the inverting amplifier and supplies current to the input/output line. A semiconductor memory sense circuit characterized by: 6. In the sense circuit according to claim 5,
The voltage controlled current drive element is an insulated gate (MI
A semiconductor memory sense circuit characterized by using an S) type transistor. 7. A plurality of word lines, a plurality of data lines provided perpendicularly to the word lines, and a plurality of memory cells provided at the intersections of the data lines and the word lines; a first decoding means for selecting at least one; and a second decoding means for selecting at least one of the plurality of data lines and connecting it to the common line; A semiconductor memory characterized in that the read information of the memory cell is output using a current/voltage conversion circuit. 8. The semiconductor memory according to claim 7, wherein the current-voltage conversion mechanism includes a differential amplifier having one input as the voltage of the input/output line and the other input as the reference voltage source;
A semiconductor memory comprising at least a voltage-controlled current drive element that is controlled by the output of the differential amplifier and supplies current to an input/output line. 9. The semiconductor memory according to claim 8,
The voltage controlled current drive element is an insulated gate (MI
A semiconductor memory characterized by using an S) type transistor. 10. In the semiconductor memory according to claim 8, the current-voltage conversion mechanism includes an inverting amplifier (inverter) that receives the voltage of the input/output line, and is controlled by the output of the inverting amplifier, and the input/output A semiconductor memory comprising at least a voltage-controlled current drive element that supplies current to a line. 11. The semiconductor memory according to claim 10, wherein an insulated gate (MIS) type transistor is used as the voltage controlled current drive element.