JPH0198263A - Manufacturing method of thin film transistor - Google Patents
Manufacturing method of thin film transistorInfo
- Publication number
- JPH0198263A JPH0198263A JP62255947A JP25594787A JPH0198263A JP H0198263 A JPH0198263 A JP H0198263A JP 62255947 A JP62255947 A JP 62255947A JP 25594787 A JP25594787 A JP 25594787A JP H0198263 A JPH0198263 A JP H0198263A
- Authority
- JP
- Japan
- Prior art keywords
- film transistor
- manufacturing
- thin film
- view
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は液晶表示素水、イメージセンサ−及び発元素示
等に利用する薄膜トランジスタ（以下ＴＦ’Ｔと称する
）の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a thin film transistor (hereinafter referred to as TF'T) used for liquid crystal displays, image sensors, light emitting devices, etc.
従来のＴＰＴ製造方法はガラス基板上にゲート電極を形
成し、ＣＶＤ法、スパッタ法、蒸着法、陽極酸化法でゲ
ート絶縁膜を成膜し、更に半導体膜を成膜し、ゲート端
子上のゲート絶縁膜、半導体膜をエツチングし、ソース
とドレイ／の各電極を形成している。In the conventional TPT manufacturing method, a gate electrode is formed on a glass substrate, a gate insulating film is formed using a CVD method, a sputtering method, a vapor deposition method, or an anodic oxidation method, a semiconductor film is further formed, and a gate electrode is formed on a gate terminal. The insulating film and semiconductor film are etched to form source and drain electrodes.
ところが従来のＴＰＴの製造方法においてゲート絶縁膜
をＣＶＤ法、スパッタ法、蒸着法、陽極酸化法で成膜し
ているので、ピノホールフリーで薄いゲート絶縁膜を量
産することが極めて困難である。However, in conventional TPT manufacturing methods, the gate insulating film is formed by CVD, sputtering, vapor deposition, or anodic oxidation, making it extremely difficult to mass-produce a thin gate insulating film free of pinholes.
本発明の目的はピノホールフリーで薄いゲート絶縁膜を
歩留りよく容易に形成しているＴＰＴの製造方法を提供
することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a TPT in which a pinothole-free thin gate insulating film can be easily formed with good yield.
この目的を達成するために、本発明のＴ Ｐ Ｔの°
製造方法は、基板上に薄膜トランジスタのゲート電極を
形成し、この電極表面を酸化剤に浸漬することによって
ゲート電極表面を酸化絶縁層に変質させる工程を具備し
て成ることを特徴とする。To achieve this objective, the present invention T P T °
The manufacturing method is characterized by comprising the steps of forming a gate electrode of a thin film transistor on a substrate, and changing the surface of the gate electrode into an oxide insulating layer by immersing the surface of the electrode in an oxidizing agent.
この発明では例えば、ＡＡ’、 ＭＯ％Ｃｒ、 Ｔａ、
Ｔｉ等の金属膜で形成したＴＰＴゲート電極＠ＨＮＯ
３、Ｈｚ ＳＯ４、Ｈ３Ｐ ＯイＨｘＣＯｓ 、Ｈ２Ｏ
２等（７） ｇ化剤マタハこれら酸化剤の混合液に浸漬
することによってゲート電極表面を酸化絶縁層に変質さ
せる。この時ゲート端子材料をゲート電極材料き異なっ
た物質例えばＩＴＯやＴＯ等にしておくことによってゲ
ート端子表面が絶縁層となることを防ぐことができる。In this invention, for example, AA', MO%Cr, Ta,
TPT gate electrode made of metal film such as Ti @HNO
3, Hz SO4, H3P Oi HxCOs, H2O
2nd grade (7) G-oxidizing agent The surface of the gate electrode is transformed into an oxidized insulating layer by immersing it in a mixed solution of these oxidizing agents. At this time, by using a material different from the gate electrode material, such as ITO or TO, as the gate terminal material, it is possible to prevent the gate terminal surface from becoming an insulating layer.
本発明の一実施例を第１図ないし第７図に基づいて説明
する。An embodiment of the present invention will be described based on FIGS. 1 to 7.
第１工程
第３図の平面図に示すように、絶縁基板上に、ＩＴＯ，
ＴＯ等のように酸化剤に浸漬してもその表面が絶縁層に
ならない材料でゲート端子９、ゲートバス２、ソースバ
ス７を形成する。As shown in the plan view of FIG. 3 in the first step, ITO,
The gate terminal 9, gate bus 2, and source bus 7 are formed of a material such as TO that does not turn the surface into an insulating layer even when immersed in an oxidizing agent.
第２工程
第３工程で得られた基板上にｋｌ、 Ｍｏ、Ｃｒ、Ｔａ
、Ｔｉ等の金属膜をスパッタ法や蒸着法で成膜したもの
をエツチングして第４図の平面図に示すように加工する
。2nd step On the substrate obtained in the 3rd step, kl, Mo, Cr, Ta
, Ti or the like is formed by sputtering or vapor deposition and then etched to process it as shown in the plan view of FIG.
第３工程
第２工程で得られた基板をＨ２（１）、 、 Ｈ，ＣＯ
，、ｋハ０８、Ｈ，Ｓ ＯいＨ３Ｐ０．やこれらの混合
液等の酸化剤に浸漬して、ゲート電極３の表面を第５図
ｆａｔの平面図及び第５図ｆｂｌの断面図のように酸化
絶縁層（こする。Third step The substrate obtained in the second step is heated with H2(1), , H,CO
,,kha08,H,SOiH3P0. The surface of the gate electrode 3 is rubbed with an oxidized insulating layer as shown in the plan view of FIG. 5 fat and the cross-sectional view of FIG. 5 fbl.
第４工程
第３工程で得られた基板上にａ−８ｉ：Ｈ等の半導体膜
をＣＶＤ法によって成膜し第６図の断面図のようにエツ
チング加工する。Fourth Step A semiconductor film such as a-8i:H is formed by CVD on the substrate obtained in the third step and etched as shown in the cross-sectional view of FIG.
第５工程
第４工程で得られた基板上にソース電極６及びドレイン
電極８を第７図の断面図のように形成する。Fifth Step A source electrode 6 and a drain electrode 8 are formed on the substrate obtained in the fourth step as shown in the cross-sectional view of FIG.
以上説明したようにＴＰＴのゲート電極表面を酸化剤に
浸漬して形成した酸化絶縁層をＴ ＦＴのゲート絶縁膜
とすることによってピンホールフリーで薄いゲート絶縁
膜でできたＴＰＴを製造することができる。その結果、
低電圧駆動で特性のよいＴＰＴを歩留りよく容易に製造
することができる等の効果がある。As explained above, by using the oxide insulating layer formed by dipping the TPT gate electrode surface in an oxidizing agent as the TFT gate insulating film, it is possible to manufacture a pinhole-free TPT with a thin gate insulating film. can. the result,
There are effects such as being able to easily manufacture TPT with good characteristics at a high yield by driving at a low voltage.
第１図は本発明により製造した薄膜トランジスタの断面
図、第２図は同薄膜トランジスタの平面図、第３図は本
発明による第１工程で得られた基板の平面図、第４図は
本発明による第２工程で得られた基板の平面図、第５図
は本発明による第３工程で得られた基板の平面図ｆａ）
と断面図（ｂ）、第６図は本発明による第４工程で得ら
れた基板の断面図、第７図は本発明による第５工程で得
られた基板の断面図である。
特許出願人 アルプス亀気株式会社
−４・FIG. 1 is a cross-sectional view of a thin film transistor manufactured according to the present invention, FIG. 2 is a plan view of the same thin film transistor, FIG. 3 is a plan view of a substrate obtained in the first step according to the present invention, and FIG. FIG. 5 is a plan view of the substrate obtained in the second step, and FIG. 5 is a plan view of the substrate obtained in the third step according to the present invention fa)
FIG. 6 is a cross-sectional view of the substrate obtained in the fourth step according to the present invention, and FIG. 7 is a cross-sectional view of the substrate obtained in the fifth step according to the present invention. Patent applicant: Alps Kamei Co., Ltd.-4.
Claims (1)
の電極表面を酸化剤に浸漬することによってゲート電極
表面を酸化絶縁層に変質させる工程を具備して成る薄膜
トランジスタの製造方法。A method for manufacturing a thin film transistor comprising the steps of forming a gate electrode of a thin film transistor on a substrate, and changing the surface of the gate electrode into an oxide insulating layer by immersing the surface of the electrode in an oxidizing agent.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62255947A JP2598922B2 (en) | 1987-10-09 | 1987-10-09 | Method for manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62255947A JP2598922B2 (en) | 1987-10-09 | 1987-10-09 | Method for manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0198263A true JPH0198263A (en) | 1989-04-17 |
| JP2598922B2 JP2598922B2 (en) | 1997-04-09 |
Family
ID=17285789
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62255947A Expired - Lifetime JP2598922B2 (en) | 1987-10-09 | 1987-10-09 | Method for manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2598922B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5186968A (en) * | 1975-01-29 | 1976-07-30 | Kyushu Nippon Electric | HANDOTAISOCHINOSEIZOHOHO |
| JPS5995514A (en) * | 1982-11-25 | 1984-06-01 | Sharp Corp | Manufacture of liquid-crystal display device |
-
1987
- 1987-10-09 JP JP62255947A patent/JP2598922B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5186968A (en) * | 1975-01-29 | 1976-07-30 | Kyushu Nippon Electric | HANDOTAISOCHINOSEIZOHOHO |
| JPS5995514A (en) * | 1982-11-25 | 1984-06-01 | Sharp Corp | Manufacture of liquid-crystal display device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2598922B2 (en) | 1997-04-09 |
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| EXPY | Cancellation because of completion of term |