JPH0199162A - Multiprocessor interruption processing system - Google Patents

Abstract

PURPOSE:To prevent the execution of a useless re-interruption by including, in a re-interruption permission command code, the identifier of a arithmetic processor that issues the very code together with the execution level of the arithmetic processor at the time of issuing. CONSTITUTION:In a re-interruption permission command code issued by the arithmetic processors 2-1, 2-2, the identifier ID7 representing the very arithmetic processor that issued said code as well as a running level value representing its execution level is included. Accordingly, such peripheral controllers 4-1-4-n as holding interruptions can know whether the arithmetic processor that permitted the re-interruption is the one at the destination of the interruption which itself is holding or not based on the identifier ID7 included in the re-interruption permission command code. Also, based on the execution level included in said code, the current execution level of the arithmetic processor can be known. As a result, any useless re-interruption can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor interrupt processing method in an information processing device in which a plurality of arithmetic processing units are connected on a bus.

[Conventional technology]

When software called multiple tasks are executed concurrently, the concept of interrupts is introduced to ensure efficient operation in information processing equipment that allows peripheral control devices used by each task to operate in parallel. ing.

In a conventional information processing device of this type that includes one arithmetic processing unit and a plurality of peripheral control devices, the arithmetic processing device puts a task that has issued an operation instruction to the peripheral control device in a waiting state and waits for other tasks. When a peripheral control device executes a task and receives an operation instruction and completes the operation according to the instruction, it sends an interrupt command code to the arithmetic processing device indicating that the operation has been completed. This interrupt command code contains an interrupt level value including the interrupt level, and when the interrupt command code is added, the processing unit compares its own execution level with the level of the interrupt caused by the interrupt command code, and If the execution level is higher, an interrupt rejection is returned to the peripheral control device that issued the interrupt command code, and the interrupt is put on hold.

When the processing unit's own execution level changes, information indicating that interrupts are permitted in the form of simultaneous notification to all peripheral control devices connected to the lotus, and the current execution level of the processing unit. Issues a re-interrupt permission command code that includes the driving level value. When the peripheral control device that is holding an interrupt receives the above-mentioned re-interrupt permission command code <jE, it compares the current execution level of the arithmetic processing unit indicated by the running level value contained therein with the level of the pending interrupt. If the interrupt level is higher, an interrupt command code is output; if the interrupt level is lower, the interrupt is held pending.

Here, the re-interrupt permission command code includes only information indicating that the interrupt is permitted, and all peripheral control devices that have received the above-mentioned re-interrupt permission command code and which have suspended interrupts are sent to the arithmetic processing unit. It is also conceivable to output an interrupt command code to the processor, and control whether or not to permit re-interruption based on the execution level of the processor and the interrupt level value included in the interrupt command code. However, if you do this, the peripheral control device whose interrupt level is lower than the execution level of the arithmetic processing unit and whose interrupts are rejected by the arithmetic processing unit will also interrupt, and such meaningless interrupts will cause task execution to be delayed. There are problems that prevent this.

[Problem that the invention seeks to solve]

In an information processing device equipped with only one arithmetic processing unit, operational efficiency can be improved by including a running level value indicating the execution level of the arithmetic processing unit in the re-interrupt permission command code as described above. It can be made high. However, in the conventional method described above, the re-interrupt permission command code only includes information indicating that interrupts are permitted and a running level value indicating the execution level of the arithmetic processing unit. If the above-described conventional method is applied as is to an information processing apparatus in which a plurality of arithmetic processing units are connected to an information processing apparatus, the following problems will occur. In other words, the re-interrupt permission command code issued from each processing unit contains only information indicating that the interrupt is permitted and the running level value of the processing unit, and the surrounding area that received the re-interrupt permission command code Since the control device cannot determine whether or not it is a re-interrupt enable command code from its own interrupt destination arithmetic processing unit, if multiple peripheral control devices have interrupts pending, it will not be possible to re-enable the interrupt. Even if the arithmetic processing unit that issued the command code is not the arithmetic processing unit that is the interrupt destination for itself, it may re-interrupt, and such meaningless interrupts impede efficient system operation. There is a problem with this.

The present invention solves the above-mentioned problems, and its purpose is to improve system operational efficiency by preventing unnecessary interrupts from peripheral control devices whose interrupts are pending.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides an information processing device in which a plurality of arithmetic processing units, a main storage device, and a plurality of peripheral control devices are interconnected via a bus. The control device performs an operation according to an operation command code applied from the arithmetic processing device via the bus,
When the operation is completed, an interrupt command code including an interrupt level value indicating the interrupt level and an identifier indicating the interrupt destination processing unit is sent to the bus, and the processing unit receives the interrupt command code applied via the bus. Based on the identifier included in the separate command code, it is determined whether the instruction is for the own processing unit, and by determining that the instruction is for the own processing unit, the execution level and the interrupt level of the own processing unit are compared. , determines whether to permit or deny the interrupt based on the comparison result, and sends a re-interrupt permission command code including its own identifier and its own execution level to the bus as its own execution level changes; Whether or not the peripheral control device holding the interrupt rejected by the arithmetic processing unit outputs the interrupt command code to the bus again based on the identifier and execution level included in the received re-interrupt permission command code. Determine.

[For production]

The re-interrupt permission command code issued by the arithmetic processing device includes an identifier indicating the arithmetic process 'AN which issued the re-interrupt permission command code, and its execution level. Therefore,
The peripheral control device that is holding the interrupt determines whether or not the arithmetic processing unit that has permitted the re-interrupt is the arithmetic processing unit that is the interrupt destination for the pending interrupt, based on the identifier included in the re-interrupt permission command code. Furthermore, since the current execution level of the arithmetic processing unit can be known based on the execution level included in the re-interrupt permission command code, meaningless re-interrupts can be eliminated.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, which includes two arithmetic processing units (IEPUs) 2-1, 2-2, a main memory device (MEM) 3, and n peripheral control devices (IOCs). )4-1
4-n are connected to the system bus 1.

The arithmetic processing units 2 to 1.2-2 read and execute software, ie, a program, stored in the main storage device 3, and perform processing intended by the program. Among the programs stored in the main storage device 3 is the peripheral control unit W4-1.
-4-n, for example, an instruction specifying data exchange between the main storage device 3 and devices under the peripheral control device, and this instruction is executed by the arithmetic processing unit 2-1.2.
-2 outputs an operation command code instructing the peripheral control devices 4-1 to 4-n to exchange data, that is, to transfer data.

FIG. 2 (al is a diagram showing an example of the structure of the operation command code output from the arithmetic processing unit 2-1.2-2;
・A destination identifier D indicating the identification number (address) on the system bus 1 of the peripheral control device that sends the operation command code is stored in ~7 bits, and a destination identifier D indicating the identification number (address) on the system bus 1 of the peripheral control device that sends the operation command code is stored in bits 8 to 15 16 bits to 23 bits contain the source identifier ID indicating the arithmetic processing unit that issued the operation command code, and 24 bits to 31 bits contain the source identifier ID indicating the processing unit that issued the operation command code. a destination identifier indicating one of the devices in 10. is accommodated.

When an operation command code in the format shown in FIG. 2(a) is added via the system bus 1, each peripheral control device 4-1 to 4
-n determines whether the operation command code is for the own peripheral control device based on the destination identifier ID stored in bits 0 to 7. Then, the peripheral control device that determines that the operation command code is for its own peripheral control device stores, for example, the main storage device 3 and the destination identifier 10 according to the command contained in bits 8 to 15 of the operation command code.
Data is transferred with the device indicated by 3, and upon completion of the operation, an interrupt command code is output to the system bus 1.

FIG. 2 (bl is a diagram showing an example of the above-mentioned interrupt command code, in which the O bit to 7 bits contain a destination identifier IDa indicating the arithmetic processing unit to be interrupted, and the 8 bits to 15 bits is the interrupt level value indicating the interrupt level given to the peripheral control device that issued the interrupt command code, 16 bits to 23 bits are the source identifier IDs indicating the peripheral control device that issued the interrupt command code, and 24 bits to 23 bits are the source identifier IDs indicating the peripheral control device that issued the interrupt command code. The 31 bits contain a source identifier IDa indicating a device under the peripheral control device.

When an interrupt command code in the format shown in FIG.
-2 determines whether or not the interrupt command code is for its own processing unit based on the destination identifier ID4 stored in the O bit to 7 bits.

The arithmetic processing unit (in this case, arithmetic processing unit 2-1) that has determined that the interrupt command code is for its own arithmetic processing unit reads the 8 bits to 8 bits of the interrupt command code.
Based on the interrupt level value contained in 15 bits, it is determined whether the interrupt level is higher than its own execution level. If it is determined that the interrupt level is higher, the interrupt is permitted; if it is determined that the interrupt level is not higher, the interrupt is rejected. The peripheral control device that issued the interrupt command code suspends the interrupt when the interrupt is rejected.

The arithmetic processing unit 2-1 which rejected the interrupt outputs a re-interrupt permission command code to the system bus 1 as its execution level changes.

Figure 2 (C1 is a diagram showing an example of a re-interrupt permission command code, in which "0" is stored in the θ bit to 7 bits, 24 bits to 31 bits, and re-interrupt permission is stored in 8 bits to 15 bits. A running level value indicating the execution level of the processing unit that issued the command code is stored in bits 16 to 23, and an EPU identifier ID? indicating the processing unit that issued the re-interrupt permission command code.

fcl from the arithmetic processing unit 2-1 to the system bus 1 in Figure 2
When the re-interrupt permission command code in the format shown in is output, the peripheral control device 4-4 that is suspending the interrupt will read the running level value contained in bits 8 to 15 of the re-interrupt permission command code. The current execution level of the arithmetic processing unit 2-1 is compared with the interrupt level of the pending interrupt, and the EPU accommodated in 16 bits to 23 bits is
Identifier ID.

Based on this, it is determined whether the arithmetic processing unit 2-1 that issued the re-interrupt permission command code is the arithmetic processing unit that is the interrupt destination for the pending interrupt. Then, only when it is determined that the interrupt level of the pending interrupt is higher than the execution level of the arithmetic processing unit 2-1 and the arithmetic processing unit 2-1 is the arithmetic processing unit to which the interrupt is to be made, for example, as shown in FIG. The interrupt command code having the format shown in b) is sent to the system bus 1 again, and the interrupt is kept in a pending state in other cases.

[Effects of the Invention] As explained above, the present invention provides a re-interrupt permission command code issued by an arithmetic processing unit that includes the identifier of the arithmetic processing unit that issued the re-interrupt permission command code and the execution level of the arithmetic processing unit at that time. The peripheral control device that is holding the interrupt will receive the interrupt of the pending interrupt based on the identifier included in the re-interrupt permission command code. and whether the interrupt level of the pending interrupt is higher than the current execution level of the processing unit based on the execution level included in the re-interrupt enable command code. As a result, meaningless re-interrupts are not performed in response to re-interrupt enable command codes issued by a processor other than the interrupt destination processor, and the interrupt level of a pending interrupt can be known. When the execution level of the arithmetic processing unit is higher than that of the first embodiment, meaningless re-interruption is not performed, and therefore system efficiency can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing an example of the configuration of each command code. In the figure, 1... system bus, 2-1.2-2.
... Arithmetic processing unit, 3... Main storage device, 4-1 to 4-
n...Peripheral control device.

Claims (1)

[Scope of Claims] In an information processing device in which a plurality of arithmetic processing units, a main storage device, and a plurality of peripheral control devices are interconnected via a bus, the peripheral control device is connected to the arithmetic processing device. perform an operation according to an operation command code applied via the bus from
When the operation is completed, an interrupt command code including an interrupt level value indicating the interrupt level and an identifier indicating the interrupt destination processing unit is sent to the bus, and the processing unit receives the interrupt command code applied via the bus. Determining whether or not the interrupt command is directed to the own processing device based on the identifier included in the interrupt instruction code, and comparing the own execution level and the interrupt level by determining that the interrupt instruction code is directed to the own processing device; It determines whether to grant or deny the interrupt based on the comparison result, and when its own execution level changes, it sends a re-interrupt permission command code including its own identifier and its own execution level to the bus; The peripheral control device that has suspended the interrupt rejected by the arithmetic processing unit determines whether to output the interrupt command code to the bus again based on the identifier and execution level included in the received re-interrupt permission command code. A multiprocessor interrupt processing method characterized by determining.