JPH0199236A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To regulate a conduction resistance and to improve noise margin by connecting a P-type transistor Tr and N-type Tr by two or more equal gate electrodes, and selecting the P-type Tr and N-type Tr to be used. CONSTITUTION:An integrated circuit device A has an N-type semiconductor region 2 formed on a P-type semiconductor substrate 1, three rows of P-type diffused regions 3a-3c, and two gate electrodes 5a, 5b formed through an insulating film between the regions 3a-3c. The device A has two P-type Trs commonly having a region 3b, three rows of N-type diffused regions 4a-4c, N-type diffused regions 4d-4f formed adjacently in three rows, and two gate electrodes 6a, 6b formed through an insulating film between the regions 4a-4f. Accordingly, the threshold value of input/output transmission characteristic at this time becomes near 1/2VDD. Thus, its noise margin is improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a complementary MOS
The present invention relates to a semiconductor integrated circuit device that improves the noise margin of a gate array.

[Conventional technology]

Conventionally, this type of complementary MOS gate array (hereinafter referred to as CM
(referred to as OS gate array) consists of multiple P-channel type MOs.
It is constructed by connecting a large number of S transistors and a plurality of N channel type MOS transistors in an array.

FIG. 4 is a general two-person NOR circuit diagram composed of CMOS transistors.

As shown in Figure 4, this two-person NOR circuit consists of P-T
P-TrPl is composed of PL and P2 as r and Nl and N2 as N-Tr.

Input terminals Vinl and Vin2 are connected to each gate of P2, and an output terminal Vout is connected to the N-TrNl and N2 side. Of the two input terminals, the input terminal Vin
2 is kept at GND potential, so P as P-Tr
2 is kept in a conductive state, N2 as an N-Tr is kept in a cut-off state, and an inverted signal of the input terminal Vinl is outputted to the output terminal Vout.

That is, in a circuit in which two P-Trs are stacked vertically, Vou when Pl and P2 as P-Trs are conductive.
Compared to the resistance value between t and VDD, N as N-Tr
1 becomes conductive, the resistance value between Vout and GND becomes a lower value. However, the input voltage Vinl and the output voltage V
Since the threshold voltage in the input/output transfer characteristic between ou and ou is determined by the ratio of the two, it is usually a value lower than 1/2 VDD.

FIG. 5 is an input/output transfer characteristic diagram of the two-person NOR circuit shown in FIG. 4.

As shown in curve C of FIG. 5, the threshold voltage in the input/output transfer characteristic of such a two-person NOR circuit is 1/2
The value is lower than .

FIG. 6 is a plan view of a CMOS gate array chip for explaining a conventional example.

As shown in FIG. 6, this chip consists of a P-type semiconductor substrate 1
N-type semiconductor region formed in 2. Three rows of P-type diffusion regions 3a to 3c are formed in this N-type region, and two gate electrodes 5a and 5b are formed between each of them with an insulating film interposed therebetween.
two P-Trs that share the P-type diffusion region 3b, and three rows of N-type diffusion regions 4a formed in the P-type semiconductor substrate 1 corresponding to these two P-Trs. ~4
A large number of N-Trs are arranged in an array, each consisting of a gate electrode 6a and 6b formed between each gate electrode 6a and 6b with an insulating film interposed therebetween, and sharing the N-type diffusion region 4b. It has a similar configuration.

FIG. 7 is a plan view of a semiconductor integrated circuit device showing an example in which the circuit shown in FIG. 4 is realized by wiring on the chip shown in FIG. 6.

As shown in FIG. 7, this integrated circuit device includes a first aluminum wiring layer (Ael) 7 formed on the chip formed in FIG. 6 via an interlayer insulating film, and this first aluminum wiring layer N7.
A second aluminum wiring layer (At?2) 9 is formed thereon with a glabella insulating film interposed therebetween. Note that 8 is a contact hole made in the interlayer insulating film between the chip and the first aluminum wiring layer 7, and 10 is a contact hole between the first aluminum wiring layer 7 and the second aluminum wiring N9. This is a through hole made in an insulating film.

Here, P-Tr composed of P-type diffusion regions 3a and 3b and gate electrode 5a corresponds to Pl in FIG. 4.

Similarly, P-type diffusion regions 3b, 3c and gate electrode 5b
P-Tr consisting of P2 and N-type diffusion region 4
The N-Tr composed of a, 4b and the gate electrode 6a is N
1, the N-Tr composed of the N-type diffusion regions 4b and 4c and the gate electrode 6b corresponds to N2, respectively.

In this way, P-Tr and N-
The widths of the P-type and N-type diffusion regions constituting the Tr in the gate electrode direction (hereinafter referred to as channel widths) were all the same. Therefore, as mentioned above, the resistance value between Vout and GND is lower than the resistance value between Vout and VDD, and the threshold voltage in the input/output transfer characteristic between the input voltage Vinl and the output voltage Vout normally becomes a value lower than 1/2VDD.

[Problem that the invention seeks to solve]

In the conventional semiconductor integrated circuit device described above, the channel widths of the P-Tr and N-Tr are all the same. Therefore, the conduction resistance of the P-Tr between the output terminal and VDD is not equal to the conduction resistance of the N-Tr between the output terminal and GND, so the threshold voltage in the input/output transfer characteristic is 1/2VDD.
However, the disadvantage is that the noise margin of the circuit is reduced.

An object of the present invention is to provide a semiconductor integrated circuit device in which the threshold voltage in the input/output transfer characteristic is brought close to 1/2 VDD, which is approximately half of the power supply voltage, and the noise margin of the circuit is significantly improved.

That is, in the present invention, since at least two or more P-Trs and N-Trs are connected by the same gate electrode, the conduction resistance is adjusted by selecting the P-Trs and N-Trs to be used. The purpose is to bring the value of the threshold voltage in the input/output transfer characteristics closer to 1/2 VDD.

[Means for solving problems]

A semiconductor integrated circuit device of the present invention has a complementary MOS gate array configured by arranging a plurality of pairs of transistors of one conductivity type and transistors of opposite conductivity type in a row. A circuit in which a plurality of gate electrodes constituting transistors of one conductivity type are connected using the same material as the gate electrodes, and gate electrodes constituting the opposite conductivity type transistors arranged in a row are made of the same material as the gate electrodes. It is configured to include at least one of a plurality of connected circuits.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a semiconductor integrated circuit device showing a first embodiment of the present invention.

As shown in FIG. 1, this integrated circuit device includes an N-type semiconductor region 2 formed in a P-type semiconductor substrate 1, and three rows of P-type diffusion regions 3a to 3c formed within this N-type region. Two gate electrodes w15a are formed between each diffusion region with an insulating film interposed therebetween.

5b, two P-Trs sharing the P-type diffusion region 3b, three rows of N-type diffusion regions 4a to 4c formed in the P-type semiconductor substrate 1, and three more rows of adjacent N-type diffusion regions 4a to 4c. N-type diffusion regions 4d to 4f formed in
a, 6b, and the N-type diffusion regions 4b, 4e.
It has a structure in which a large number of four N-Trs each sharing the same number are arranged in an array. In other words, the four N
-Tr has a shape in which two transistors are connected by two gate electrodes 6a and 6b. Furthermore, in order to realize a circuit similar to the two-man NOR circuit shown in FIG. A first Al wiring layer 7, a contact hole 8 formed in the interlayer insulating film, a second Al wiring layer 9 deposited on the first Al wiring layer 7 via an insulating film between the eyebrows, and a through-hole. A hall 1o is provided.

Here, P-Tr composed of P type diffusion regions 3a, 3b and gate electrode 5a corresponds to Pl shown in FIG. 4, and is similarly composed of P type diffusion regions 3b, 3C and gate electrode 5b. The P-Tr to be
The N-Tr composed of the gate electrode 6b and the gate electrode 6a corresponds to N1, and the N-Tr composed of the N-type diffusion regions 4b and 4c and the gate electrode 6b corresponds to N2.

Looking at the channel width of the transistor with this configuration, the channel width of N1 as an N-Tr is narrower than the channel width of Pl and P2 as P-Tr, so the vertically stacked transistors P1 and P2 are conductive. Compared to the resistance value when the transistor N1 is turned on, the resistance value when the transistor N1 is turned on becomes a value closer to the above-mentioned resistance value than before. Therefore, the value of the threshold voltage in the input/output transfer characteristic at this time becomes a value close to 1/2 VDD, and the noise margin in the circuit becomes large.

FIG. 2 is a plan view of a semiconductor integrated circuit device showing a second embodiment of the present invention.

As shown in FIG. 2, the difference between this second embodiment and the first embodiment described above is that in the first embodiment, N
In addition to Nl and N2 as -Trs, an N-Tr with a narrower channel width is added. That is, the two P-TrPl and P2 in the first embodiment are the same, but when looking at the N-Tr, the three rows of N-type diffusion regions 4a to 4c formed in the P-type semiconductor substrate 1 and It is composed of N-type diffusion regions 4d to 4f and 4g to 41 formed in three rows next to them, and two gate electrodes 6a and 6b formed between each of the diffusion regions with an insulating film interposed therebetween. Said N
Type diffusion regions 4b, 4e.

The difference is that it has six N-Trs that each share 4h. Further, this second embodiment has diffusion regions 4a and 4.
g, 4b and 4h, and 4c and 41 are connected by the first Al wiring layer 7 through the contact hole 8, so that the conduction resistance is lower than that of the first embodiment.
Since the conduction resistance between r and N-Tr can be made closer, the value of the threshold voltage in the input/output transfer characteristic can be brought closer to a value close to 1/2 VDD, and the noise margin can be further improved. .

Figure 3 shows the two-man power N in the above two embodiments of the present invention.
It is an input-output transfer characteristic diagram of an OR circuit.

As shown in FIG. 3, characteristic a indicates the input/output transfer characteristic in the first embodiment described above, and characteristic a indicates the input/output transfer characteristic in the second embodiment described above. As can be seen, the threshold voltage in the second embodiment is approximately 1/2 VDD, which is significantly improved compared to the conventional threshold voltage (characteristic C) shown in FIG. ing.

〔Effect of the invention〕

As explained above, the semiconductor integrated circuit device of the present invention includes
A circuit in which a plurality of gate electrodes forming first conductivity type transistors arranged in a row are connected using the same material as the gate electrodes in a CMOS gate array, and a gate forming a reverse conductivity type transistor arranged in a row. By having at least one of the gate electrode and a circuit made of the same material connected to a plurality of electrodes, the number of transistors of one conductivity type and opposite conductivity type used depending on the circuit configuration can be reduced to 311.
113, and the noise margin can be improved.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a semiconductor integrated circuit device showing a first embodiment of the invention, FIG. 2 is a plan view of a semiconductor integrated circuit device showing a second embodiment of the invention, and FIG. 3 is a plan view of a semiconductor integrated circuit device showing a second embodiment of the invention. Input/output transfer characteristic diagram of the two-man power NOR circuit in the above two embodiments, 4th
The figure shows a general two-person N configured with CMO3) transistors.
FIG. 5 is an input/output transfer characteristic diagram of the two-man NOR circuit shown in FIG. 4, FIG. 6 is a plan view of a CMOS gate array chip to explain a conventional example, and FIG. 7 is an OR circuit diagram. FIG. 6 is a plan view of a semiconductor integrated circuit device showing an example of a conventional semiconductor integrated circuit device in which the circuit shown in FIG. 4 is implemented on the chip shown in FIG. 6; 1... P-type semiconductor substrate, 2... N-type semiconductor region, 3
a to 3C...P type diffusion region, 4a to 41...N type diffusion region, 5a, 5b...-P-Tr gate electrode, 6a,
6b... N-Tr gate electrode, 7... First gate 2
Wiring layer, 8... Contact hole, 9... Second A
e wiring layer, 10... through hole.

Claims (1)

[Claims] In a semiconductor integrated circuit device having a complementary MOS gate array configured by arranging a plurality of pairs of transistors of one conductivity type and opposite conductivity type transistors in a row, gate electrodes forming the transistors of the one conductivity type arranged in a row. A circuit in which multiple gate electrodes are connected using the same material,
1. A semiconductor integrated circuit device comprising at least one of a plurality of gate electrodes forming the reverse conductivity type transistors arranged in a row and a circuit formed by connecting a plurality of gate electrodes and the same material.