JPH0199244A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH0199244A
JPH0199244A JP62257692A JP25769287A JPH0199244A JP H0199244 A JPH0199244 A JP H0199244A JP 62257692 A JP62257692 A JP 62257692A JP 25769287 A JP25769287 A JP 25769287A JP H0199244 A JPH0199244 A JP H0199244A
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
case
circuit device
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62257692A
Other languages
Japanese (ja)
Inventor
Kenji Ogawa
小川 憲治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62257692A priority Critical patent/JPH0199244A/en
Publication of JPH0199244A publication Critical patent/JPH0199244A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00Constructional details of devices covered by this subclass
    • H10F77/50Encapsulations or containers

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To obtain a semiconductor integrated circuit device which is easily screened by providing an observation window made of transparent ceramics or glass on an inner semiconductor chip. CONSTITUTION:An observation window 6 made of transparent ceramics of glass is provided on a semiconductor chip 2 in a case. Then, the chip 2 can be observed from an exterior in a state that a protection cover 7 is not attached during screening. Accordingly, surface change, i.e., a crack, a discolor, bent of wiring, etc., generated in the chip 2 due to mechanical, electrical stress to be applied can be detected by a visual observation. Thus, a semiconductor integrated circuit device which can be easily screened is obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit device.

〔従来の技術〕[Conventional technology]

第3図および第4図はそれぞれ従来の高信頼性半導体集
積回路装置の断面構造図で、セラミックケース14ある
いは金属カンケース11内に半導体チップ2をマウント
シ、ポンディング・ワイヤー3によシケースの端子4と
チップ間を接続し、セラミックキャップ15あるいは金
属製キャップ16をケースに熱圧着もしくは溶接によっ
て取り付は封止した構造を有する。この場合、封止材に
は信頼性の高いセラミックまたは金属製のケースが用い
られ、さらに1機械的、熱的、電気的試験を含むさまざ
まのスクリーニングを実施して不良品を取プ除くことに
よシ、高い信頼性を得ている。
3 and 4 are cross-sectional structural diagrams of conventional highly reliable semiconductor integrated circuit devices, respectively, in which a semiconductor chip 2 is mounted in a ceramic case 14 or a metal can case 11, and a bonding wire 3 is connected to a terminal of the case. 4 and the chip, and a ceramic cap 15 or a metal cap 16 is attached to the case by thermocompression bonding or welding for sealing. In this case, a highly reliable ceramic or metal case is used as the encapsulant, and a variety of screenings including mechanical, thermal, and electrical tests are performed to eliminate defective products. Yes, it has achieved high reliability.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述したように従来の高信頼性半導体集積回路装置は、
さまざまのスクリーニングを施こすととくより高い信頼
性を得ているが、これらのスクリーニングは、半導体チ
ップ2に対して機械的、熱的、電気的ストレスを加える
ことによシ、チップを早期に劣化させ、内在する不良を
試験期間内に顕在化させることを目的とするものである
。従って、スクリーニングの度合によりては、良品の素
子そのものも悪化させる可能性をも含んでおシ、スクリ
ーニングによって、完全に内在する不良が顕在化したか
どうかを判定することは困難である。
As mentioned above, conventional high reliability semiconductor integrated circuit devices are
Higher reliability has been obtained by performing various screenings, but these screenings do not apply mechanical, thermal, or electrical stress to the semiconductor chip 2, which may cause the chip to deteriorate prematurely. The purpose of this test is to expose any underlying defects within the testing period. Therefore, depending on the degree of screening, there is a possibility that even a good element itself may be deteriorated, and it is difficult to determine whether or not an inherent defect has completely surfaced through screening.

このため真に高い信頼性を得るためには、非常に多くの
素子にくり返しスクリーニングを加え、生き残った少数
の素子を使用するような選別法しか実施することができ
ない。しかも、得られた素子のいずれが将来不良になる
か伺うかさえ判定する〔問題点を解決するための手段〕 本発明によれば、ケース内に半導体チップを載置する構
造の半導体集積回路装置は、前記ケース内部の半導体チ
ップ上に透明なセラミックまたはガラスからなる観察窓
を具備して形成されることを含む。
Therefore, in order to obtain truly high reliability, the only selection method that can be used is to repeatedly screen a large number of devices and use a small number of surviving devices. Moreover, it is even determined whether any of the obtained elements will become defective in the future (means for solving the problem). According to the present invention, a semiconductor integrated circuit device having a structure in which a semiconductor chip is placed in a case The method includes forming an observation window made of transparent ceramic or glass on the semiconductor chip inside the case.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を示す半導体集積回路装置の
断面構造図である。本実施例によれば、ネジ穴を設けた
セラミックケース1の内に半導体チップ2をマウントし
、ボンディングワイヤー3によりてチップ2と端子4と
を接続し、透明なセラミックあるいはガラスの窓6を設
けたキャップ5を熱圧着で取り付けて封止し、さらKこ
のキャップ全体を覆うように保護カバー7が取り付はネ
ジ8によってケース1に取シ付けられる。ここで、9お
よび10はナツトおよび座金をそれぞれ示す。
FIG. 1 is a cross-sectional structural diagram of a semiconductor integrated circuit device showing one embodiment of the present invention. According to this embodiment, a semiconductor chip 2 is mounted inside a ceramic case 1 provided with screw holes, the chip 2 and terminals 4 are connected by bonding wires 3, and a transparent ceramic or glass window 6 is provided. A protective cover 7 is attached to the case 1 with screws 8 so as to cover the entire cap. Here, 9 and 10 represent a nut and a washer, respectively.

上記実かq例が示す構造の本発明半導体集積回路装置は
、スクリーニング中保饅カバー7を取り付けない状態で
半導体チップ2を外部から観察可能な状態としておくこ
とにより加えられる機械的、熱的、電気的ストレスによ
ってチップ2に生じる表面的変化、すなわちり2ツク、
変色、配線のくびれ、変形およびボンディング・ワイヤ
ー3の変形停を目視により検出できるので、これらの変
化により電気的不良が発生する以前に、表面観察によυ
これらの変化の生じた素子を取シ除くことが可能となる
。また、レーザー・スキャンニングφマイクロスコープ
を用いることにより、レーザ光を照射しながら動作状態
において外部端子には表われない素子内部の任意の部分
における電気的特性変化も観察できるので、表面的変化
以外にチップ内部の特性変化に起因する不良も事前に除
去することが可能となる。
The semiconductor integrated circuit device of the present invention having the structure shown in the above-mentioned examples q and 9 is capable of reducing mechanical, thermal, and Surface changes caused to the chip 2 due to electrical stress, i.e.
Discoloration, constriction of the wiring, deformation, and deformation of the bonding wire 3 can be visually detected, so surface observation can detect υ before electrical defects occur due to these changes.
It becomes possible to remove the elements in which these changes have occurred. In addition, by using a laser scanning φ microscope, it is possible to observe changes in electrical characteristics in any part of the device that does not appear on the external terminals during operation while irradiating laser light. Furthermore, defects caused by changes in characteristics inside the chip can also be eliminated in advance.

以上述べてきたように、光学的観察を併用してスクリー
ニングを実施した後、チップ2に対する外部光の影響を
除き、窓部分を保護するためセラミック保糎カバー7を
取り付ける。保護カバー7の取り付けに際しては、チッ
プ2に対する悪影響を防ぐため、熱ストレスを与えない
ように取り付はネジ8によって保護カバー7はケース1
に取り付けられる。この際、当然機械的ストレスが加わ
らないよう((ネジの締め付は圧力は、十分低い値にコ
ントロールし、緩衝効果が得られる様柔らかな材質の座
金10を用いるか、必要に応じバネ等を介することが望
ましい。
As described above, after performing screening using optical observation, the ceramic adhesive cover 7 is attached to remove the influence of external light on the chip 2 and to protect the window portion. When installing the protective cover 7, the protective cover 7 is attached to the case 1 using screws 8 to prevent heat stress from being applied to the chip 2.
can be attached to. At this time, of course, be careful not to apply mechanical stress. It is preferable to intervene.

第2図は本発明の他の実施例を示す半導体集積回路装置
の断面構造図である。本実施例によれば半導体テップ2
は金属カンケース11内にマウントされボンディング・
ワイヤー3によシ端子4とチップ2が接続され、前実施
例と同様に透明なセラミックあるいはガラスの窓6を設
けた金属製キャップ12の溶接で封止され、さらにキャ
ップ全体を覆うように金属製保護カバー13がカシメに
よってケース11に取り付けられる。
FIG. 2 is a cross-sectional structural diagram of a semiconductor integrated circuit device showing another embodiment of the present invention. According to this embodiment, the semiconductor chip 2
is mounted inside the metal can case 11 and bonded.
The terminal 4 and the chip 2 are connected to the wire 3 and sealed by welding a metal cap 12 provided with a transparent ceramic or glass window 6 as in the previous embodiment. The protective cover 13 is attached to the case 11 by caulking.

本実施例が示す構造の半導体集積回路装置も、前実施例
と同様に光学的叢察を併用したスクリーニングを実権す
ることができる。このときもスクリーニングを終了した
後、金属製保護カバー13をストレスを加えない様にカ
シメで取り付けられる。しかし、この金属製保護カバー
13は、ケース1との間を封止する必要はないので、取
り付は後ハズレない程度に取シ付けられていれば良く、
多少のガタがあっても十分である。また金、成製に、限
らず必要番(応じ異色の樹脂材を少量充填しておいても
良い。
The semiconductor integrated circuit device having the structure shown in this embodiment can also perform screening using optical observation in conjunction with the previous embodiment. At this time as well, after the screening is completed, the metal protective cover 13 is attached by caulking without applying stress. However, this metal protective cover 13 does not need to be sealed between it and the case 1, so it is only necessary to attach it to the extent that it will not come loose later.
It is enough even if there is some play. In addition, it is not limited to gold or synthetic materials, but may also be filled with a small amount of resin material of a different color depending on the required number.

以上述べてきた窓をもったケースについては、すでに紫
外線消去形プログラマブル・リードオンリーメモリー、
あるいは発光ダイオード、半導体レーザー等のケースと
して幅広く用いられており信頼性についても十分な実績
が得られているのでケースとしての信頼性に同等問題は
ない。また、保護カバーの取シ付けにはいずれも機械的
な手段を用いた場合についてのみ述べたが、悪影響を与
えない範囲であれば、熱圧着溶接あるいは接着等の方法
を当然用いてよい。
Regarding the case with the window mentioned above, there are already ultraviolet erasable programmable read-only memories,
Alternatively, it is widely used as a case for light emitting diodes, semiconductor lasers, etc., and has a sufficient track record of reliability, so there is no problem with the reliability of the case. In addition, although only the cases in which mechanical means are used to attach the protective cover have been described, methods such as thermocompression welding or adhesive bonding may of course be used as long as they do not cause any adverse effects.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように、本発明によればスクリーニ
ング中光学的および目視的観察可能なケース構造が採用
されているので、従来に比べよシ信頼性の高い半導体集
積回路装置をより安価に供給し得る効果を有する。
As explained in detail above, according to the present invention, a case structure that allows optical and visual observation during screening is adopted, so semiconductor integrated circuit devices with higher reliability can be provided at a lower cost than in the past. It has a possible effect.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す半導体3i!、積回路
装置の断面構造図、第2図は本発明の他の実施例を示す
半導体集積回路vctの断面構造図、第3図および第4
図はそれぞれ従来の高信頼性半導体集積回路装置の断面
構造図である。 1.14・・・・・・セラミックeケース、2・・・・
・・半導体チップ、3・・・・・・ボンディング・ワイ
ヤー、4・・・・・・端子、5.15・・・・・・セラ
ミック・キャップ、6・・・・・・ガラス窓、7・・・
・・・セラミック保護カバー、8・・・・・・ネジ、9
・・・・・・ナツト、10・・・・・・座金、11・・
・・・・金属カンケース、12.16・・・・・・金属
製キャップ、13・・・・・・金属製保護カバー。 代理人 弁理士  内 原   音 4舗G 第 1 図 / 第2 図 第3 回 4    tf 第4図
FIG. 1 shows a semiconductor 3i! which shows an embodiment of the present invention. , FIG. 2 is a cross-sectional structural diagram of a semiconductor integrated circuit vct showing another embodiment of the present invention, FIGS.
Each figure is a cross-sectional structural diagram of a conventional highly reliable semiconductor integrated circuit device. 1.14...Ceramic e case, 2...
... Semiconductor chip, 3 ... Bonding wire, 4 ... Terminal, 5.15 ... Ceramic cap, 6 ... Glass window, 7.・・・
...Ceramic protective cover, 8...Screw, 9
...Natsuto, 10...Washer, 11...
...Metal can case, 12.16...Metal cap, 13...Metal protective cover. Agent Patent Attorney Uchihara Oto 4 G Figure 1/ Figure 2 3rd session 4 tf Figure 4

Claims (1)

【特許請求の範囲】[Claims]  ケース内に半導体チップを載置する構造の半導体集積
回路装置において、前記ケースは内部の半導体チップ上
に透明なセラミックまたはガラスからなる観察窓を具備
して形成されることを特徴とする半導体集積回路装置。
A semiconductor integrated circuit device having a structure in which a semiconductor chip is placed in a case, wherein the case is formed with an observation window made of transparent ceramic or glass on the semiconductor chip inside. Device.
JP62257692A 1987-10-12 1987-10-12 Semiconductor integrated circuit device Pending JPH0199244A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62257692A JPH0199244A (en) 1987-10-12 1987-10-12 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62257692A JPH0199244A (en) 1987-10-12 1987-10-12 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH0199244A true JPH0199244A (en) 1989-04-18

Family

ID=17309783

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62257692A Pending JPH0199244A (en) 1987-10-12 1987-10-12 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0199244A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5087964A (en) * 1989-10-31 1992-02-11 Mitsubishi Denki Kabushiki Kaisha Package for a light-responsive semiconductor chip

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5087964A (en) * 1989-10-31 1992-02-11 Mitsubishi Denki Kabushiki Kaisha Package for a light-responsive semiconductor chip

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