JPH0199251A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the rapidity, margin of an operation by respectively applying threshold voltages having different substrate effect coefficients to transistors. CONSTITUTION:A field oxide film 2 is formed on the main face of a p-type semiconductor substrate 1 made of a silicon substrate, and transistors TrA, TrB are formed on two active regions. The TrA is formed of n<+> type impurity regions 6a, 6b to become source, drain regions, n<-> type impurity regions 7a, 7b for connecting thereto, a gate oxide film 5a on the main face of the substrate 1, and a gate electrode 4a thereon. On the other hand, the TrB is formed of the same configuration as that of the TrA, but its gate length is shorter, and further formed in a p<+> type well 3 formed on the main face of the substrate 1. That is, the concentration of the channel of the TrA is the concentration p-type of the substrate 1, and the concentration of the channel of the TrB becomes p<+> type.

Description

[Detailed description of the invention] [Industrial use bone,! ] The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device constituted by a transistor having an LDD structure for relaxing a drain electric field.

[Prior Art] In recent years, there have been remarkable attempts to improve the performance of MOS field effect transistors, and efforts are being made to reduce the gate length and channel length. When the channel length is reduced to about 1.5 μm or less by this shortening of the channel, the proportional reducing agent works, and the thickness of the gate oxide film is reduced to about 200 to 300 μm. As a result, a high electric field is created in the channel region, hot carriers are generated, and hot carrier injection into the gate oxide film and breakdown voltage drop occur.

The hot carrier injection phenomenon causes characteristic deterioration such as a change in threshold voltage over time and a decrease in mutual conductance. In order to prevent the deterioration of transistor characteristics due to such short channels, LDD (Lightly
A transistor having a doped drain-3source structure has been developed.

FIG. 3 is a schematic diagram of an MO3 type transistor having an LDD structure.

In the figure, n+ type impurity regions 6a and 6b, which become source or drain regions, are formed in an active region surrounded by a field oxide film 2 formed on the main surface of a p-type semiconductor substrate 1 made of a silicon substrate or the like. A gate electrode 4 is formed on the main surface of the conductive substrate 1 sandwiched between the n+ type impurity regions 6a and 6b via a gate oxide film 5, and side walls are formed on both sides of the gate electrode 4 and the gate oxide film 5. 8
is formed. In the region of the semiconductor substrate 1 under the sidewall 8, low concentration n- type impurity regions 7a and 7b are formed so as to be in contact with the n+ type impurity regions 6a and 6b, forming an LDD structure. The drain region is divided into n-/n+ layers by the n- type impurity regions 7a and 7b, and the n- layer relaxes the drain electric field, increases the breakdown voltage, and further prevents hot carrier injection.

On the other hand, as the gate length is shortened, the depletion layers generated when voltage is applied to each of the source and drain regions come closer to each other, and eventually these depletion layers overlap. That is, a punch-through phenomenon occurs between the source and drain regions, causing a large leakage current to flow, resulting in a so-called short channel effect, which poses a serious problem to the operating characteristics of the transistor. The lower the concentration of the substrate, the greater the spread of the depletion layer, so increasing the concentration of the semiconductor substrate is important for transistors aiming for short channels in order to prevent the punch-through phenomenon.

Against this background, in transistors having an LDD structure, it has been conventional practice to increase the concentration of the semiconductor substrate in order to suppress the above-mentioned short channel effect.

[Problems to be Solved by the Invention] Generally, the threshold voltage vTH of an n-type MOS transistor is expressed by the following equation.

T14 −VF a +2+ilp P +BK 2<6F
P + lvB al... (1) where, vFa: flat band voltage (work function φ of gate metal
1 and the work function φ of silicon) φ, P; Fermi potential (difference between the Fermi level of silicon and the intrinsic Fermi level) B, two-substrate effect coefficient VaB: bias voltage of the semiconductor substrate, and substrate effect coefficient B is expressed by the following formula.

BK-tOx/ε. xmNA−(2) where, tox: thickness ε of the gate oxide film. X = dielectric constant q of gate oxide film: charge bulk εS+' dielectric constant NA of silicon: impurity concentration of semiconductor substrate As is clear from equations (1) and (2), vTH increases as substrate effect coefficient B increases. The more it gets, the bigger it gets. That is, it means that the threshold voltage of the transistor increases as the impurity concentration NA of the semiconductor substrate increases.

From the above, in a semiconductor integrated circuit having a transistor with an LDD structure, it is necessary to increase the impurity concentration of the semiconductor substrate in order to suppress the short channel effect, and as a result, the transistor included in the semiconductor integrated circuit The threshold voltages of all of them are higher than conventional ones. However, semiconductor integrated circuits are composed of transistors that share many functions, and there are some transistors that cause problems due to an increase in threshold voltage.

FIG. 4 shows an inverter circuit to which an input signal is applied to the gate.

In the figure, P-type MoS transistors Q+ and Q are connected between power supply voltage VCC and node N1 connected to output signal v01.
2 is connected to the transistor Q.

The gate of is grounded. An N-type MOS transistor Q3 having one conduction terminal grounded is connected to the other side of the node N, and an input signal V is branched and connected to the gates of the transistor Q2 and the transistor Q. Input signal■,
is at a low level, transistor Q1. Since Q2 is turned on, node N is at VCC. Next, when the input signal V changes to high level, the transistor Q2
is turned off, transistor Q is turned on, and the potential of node N changes from vcc to 0. However, if the threshold voltage vT8 of transistor Q is too high, transistor Q
, the gate voltage for turning on, that is, the input signal V
The voltage value at the high level of , becomes even higher. Therefore, if the threshold voltage of transistor Q, is low, the margin that input signal V, originally had with respect to the minimum voltage value for turning on transistor Q, will increase as the threshold voltage of transistor Q, increases. Therefore, it decreases.

On the other hand, generally in a MOS type semiconductor integrated circuit, a MOS transistor connected to an input terminal or an output terminal, that is, a human input signal V in this figure.

Since the leakage current of transistor Q (an N-type MOS connected to transistor Q) is specified, the gate length of transistor Q is formed to be relatively long in consideration of manufacturing variations. Therefore, the transistor Q3 surrounded by the broken line in this figure
Originally, the punch-through phenomenon due to the expansion of the depletion layer occurring in the source and drain regions is difficult to occur, and an increase in the threshold voltage is extremely disadvantageous in terms of circuit operation.

FIG. 5 shows a circuit including a load transistor acting as a source follower.

In the figure, an N-type MOS transistor Q4 is connected between the power supply voltage VCC and a node N2 connected to the output signal v02, and an N-type MOS transistor Qs is connected between the node N2 and the ground power supply.

A high level control signal vH and a low level control signal vL are connected to the gates of the transistors Q* and Qs, respectively. In this case, when the high-level control signal vH is applied, the transistor Q turns on, and the power supply voltage VCC is output as the output signal v02 via the transistor Q4, but in order for the transistor Q4 to remain on, the node N
The high level control signal vH must be higher than the potential of the transistor Q4 by the threshold voltage vTM of the transistor Q4. That is, if the high level control signal vH is constant, the "H" level of the output signal v02 is lowered by the threshold voltage. Therefore, the threshold voltage of the transistor Q4 surrounded by the broken line in the figure is desired to have a smaller value so as not to lower the "H" level of the output signal vo2. Furthermore, in this figure, when transistor Q is on, the source potential, ie, the potential V of node N2, increases, so that the bias voltage to the ground power supply, ie, the substrate, increases for transistor Q4. Therefore, the substrate bias voltage IVaal in equation (1) effectively corresponds to IVaal+Vs, and the threshold voltage VTII increases more and more.

FIG. 6 shows a control circuit for the boosted signal.

In the figure, the boosted signal vH9 is boosted to a level higher than the power supply voltage.
to control boost signal vH2, N-type M'OS)
Rankstar Q7 is boosted signal V. , and the control boost signal Vll
2. Also, the control signal vc is an N-type MO
Connected to the gate of transistor Q7 via S transistor Q6. Power supply voltage V is applied to the gate of transistor Q6.
When CC is connected, power supply voltage VCC is applied to the gate of transistor Q6 to turn on transistor Q6, and control signal VC is applied to the gate of transistor Q to turn on transistor Q7. However, if the threshold voltage of transistor Q7 is high, the rise in the source potential of transistor Q will be suppressed.
The conductance of the control boost signal Vjl2 with respect to the boost signal VH+ is reduced. Therefore, it is desirable that the threshold voltage of the transistor Q7 surrounded by the broken line in the figure has a low value.

FIG. 7 shows the circuit of the decoder output section.

In the figure, a P-type M is connected between the power supply voltage Vcc and the ground power supply.
OS transistor Q8 and N-type MOS transistor Q
s, Q+. , Qll are connected in series. A precharge signal VP is connected to the gate of transistor Q8, and transistor Q9. Address 1 signal VA++, address 2 signal VA2, and address 3 signal VA3 are connected to the gates of Q+o and Q++, respectively. transistor Q8
A node N between the transistor Q9 and the transistor Q9 is connected to the decode output Vp.

In this case, the potential of the node N before the address signal VA, ~vA, is inputted is the power supply voltage VCC, so if the threshold voltage of the transistor Q91QIO is high, the gate voltage for turning them on, That is, the voltage required as the address signal VA I + vA 2 becomes even higher. Transistor Q9. Q. ,Q,1
After all are turned on, the source potential, that is, node N
Since the potential of , becomes the ground potential, the above problem is solved.

Therefore, at the start of operation, if the threshold voltage of the transistor surrounded by the broken line is high, it will be disadvantageous in terms of operation.

FIG. 8 is a circuit diagram of the memory cell portion of the dynamic RAM.

In the figure, an N-type MO3) transistor Q1□ and a capacitor C are connected in series between the bit line BL and the cell plate power supply V, and the gate of the transistor Q1□ is connected to the word line W.
Connected to L. During writing, the transistor Q12 is turned on by applying a predetermined voltage to the word line WL,
The potential of the bit line BL is stored in the capacitor C via the transistor Q+2. At the time of read ratio, the charges accumulated in the capacitor C are taken out to the bit line BL by turning on the transistor QI2, so that the larger the amount of accumulated charges, the higher the reliability of the memory. However, if the threshold voltage of transistor Q+2 is high, the potential level applied to capacitor C is lowered by that amount compared to the potential level of bit line BL. Since this decrease in potential level results in a decrease in the amount of charge stored in the capacitor C, it is desirable that the threshold voltage of the transistor QI2 surrounded by the broken line has a low value.

As is clear from the circuit examples above, there are transistors that perform various functions and roles in semiconductor integrated circuits, and among them there are many transistors whose threshold m voltage must be prevented from increasing. .

The present invention has been made to solve these problems, and an object of the present invention is to provide a semiconductor integrated circuit device in which the threshold voltages of transistors are varied depending on the functions of the transistors.

[Means for Solving the Problems] A semiconductor integrated circuit device according to the present invention includes: a first semiconductor substrate having a first substrate effect coefficient and a first main surface; LDD formed on the first main surface of
a second semiconductor substrate having a second substrate effect coefficient different from the first substrate effect coefficient and a second principal surface;
and a second transistor having an LDD structure formed on the main surface of the transistor.

[Operation] In the present invention, different substrate effect coefficients provide different threshold voltages to each transistor.

[Example] FIG. 1 is a schematic sectional view showing an embodiment of the present invention.

In the figure, a p-type semiconductor substrate 1 made of a silicon substrate
A field oxide film 2 is formed on the main surface of the field to secure two active regions, and transistors Tr and A are provided in each active region.
and transistor Tr.

B is formed. The transistor Tr, A has an n+ type impurity region 6a which becomes a source or drain region.

6b, n-type impurity regions 7a and 7b connected to n+-type impurity regions 6a and 6b, and n-type impurity regions 7a and 7b.
It consists of a gate oxide film 5a on the main surface of the semiconductor substrate 1 sandwiched between the two, and a gate electrode 4a on the gate oxide film 5a. Sidewalls 8a and 8b formed on both sides of the gate electrode 4a and the gate oxide film 5a form the n+ type impurity region 6.
This served as a mask during impurity implantation to form portions a and 6b. On the other hand, the transistors Tr and B have the same structure as the transistors Tr and A, but have a shorter gate length and are formed in a p+ type well 3 formed on the main surface of the p type semiconductor substrate 1. That is,
The concentration of the channel portions of the transistors Tr and A is the concentration p of the semiconductor substrate 1, but the concentration of the channel portions of the transistors Tr and B is p+. Therefore the transistor T
r and B suppress the expansion of the depletion layer by increasing the concentration of the substrate to prevent the bunch-through phenomenon, which is a problem due to the shortening of the gate length, and the transistor Tr.

A prevents the threshold voltage from increasing by not increasing the concentration of the substrate. Therefore, if the transistors Tr and A having such a configuration are applied to the transistors surrounded by broken lines in FIGS. 4 to 8, various problems caused by an unnecessary increase in threshold voltage can be solved.

FIG. 2 is a schematic sectional view showing another embodiment of the invention.

In the figure, the configurations of transistors Tr, A and transistors Tr, B are the same as in FIG. 1, but in this figure, transistors Tr, A.

Both Tr and B are formed on the main surface of the p-type semiconductor substrate 1.
+ Provided in the 10-shaped well, and further transistors Tr, A
is provided in a p-type well 10 formed within the p+ ten-shaped well 9. Therefore, the substrate concentration of transistors Tr, A is p, and the substrate concentration of transistors Tr, B is p+
Thus, the same effect as the transistors Tr, A, Tr, and B in FIG. 1 is achieved.

Note that in both of the above embodiments, the combination of wells is specified, but the combination is not limited to these. For example, the transistors Tr, A, Tr, and B may be provided in separate wells formed in the semiconductor substrate 1. Needless to say, the same effect can be achieved.

Furthermore, in both of the above embodiments, the case where an N-type MOS transistor is used is explained, but it can also be applied to a P-type MOS transistor by appropriately selecting the conductivity type of the semiconductor substrate and the applied potential. be effective.

[Effects of the Invention] As explained above, the present invention provides different substrate effect coefficients to the respective substrates of transistors having an LDD structure that are required to operate at different threshold voltages. It can be operated at a threshold voltage, and has the effect of contributing to high-speed operation and improvement of operating margin.

[Brief explanation of the drawing]

Fig. 1 is a schematic sectional view showing one embodiment of the present invention, Fig. 2 is a schematic sectional view showing another embodiment of the invention, and Fig. 3 is a schematic sectional view showing an embodiment of the present invention.
A schematic configuration diagram of an MO5 type transistor having a DD structure,
Fig. 4 shows an inverter circuit to which a human input signal is applied to the gate, Fig. 5 shows a circuit including a load transistor acting as a source follower, and Fig. 6 shows a boosted signal control circuit. , FIG. 7 is a diagram showing a circuit of a decoder output section, and FIG. 8 is a diagram showing a circuit of a memory cell section of a dynamic RAM. In the figure, 1 is a semiconductor substrate, 3 is a p-type well, 4a
, 4b is a gate electrode, 5a and 5b are gate oxide films, 6a
6d are n+ type impurity regions, 7a to 7d are n− type impurity regions, 9 is a p-type well, and 10 is a p-type well. In each figure, the same reference numerals indicate the same or corresponding parts. Akira 10 IQ 9 volumes Ushibar No. 3, 4th section L Date of Showa Year, Month, Day, Mr. Commissioner of the Patent Office ゛弼]
'1, Indication of the incident Patent application No. 62-258617
No. 2, Name of the invention Semiconductor integrated circuit device 3, Person making the amendment Representative Moriya Shiki 4, Agent 5, Scope of claims and Detailed description of the invention column 6 of the specification to be amended, Amendment Contents (1) The scope of claims in the specification is as attached. (2) The text from page 14, line 6 to page 14, line 14 of the specification is corrected as follows. A semiconductor integrated circuit device according to the present invention includes a first semiconductor region having a main surface and a first substrate effect coefficient, and an LDD structure formed on the main surface of the first semiconductor region. a first transistor; a second semiconductor region having a main surface and a second substrate effect coefficient different from the first substrate effect coefficient; and an L formed on the main surface of the second semiconductor region.
and a second transistor having a DD structure, and the first and second semiconductor regions are formed on the same semiconductor substrate. (3) "Each substrate" on page 17, line 19 of the specification is corrected to "each semiconductor region." 2, Claim (1) A first semiconductor 11M having a main surface and a first substrate effect coefficient, and an LDD (lightly doped) formed on the main surface of the first semiconductor region. a first transistor having a drain/source (drain/source) structure; and a second transistor having an LDD structure formed on the main surface of the second semiconductor region. A semiconductor integrated circuit device, wherein the first and second semiconductor regions are formed on the same semiconductor substrate. (2) The first semiconductor region has a first substrate concentration, the second semiconductor color bar has a second substrate concentration, and the first substrate concentration and the second substrate concentration are different from each other. 2. The semiconductor integrated circuit device according to claim 1, wherein the first and second substrate effect coefficients have different values due to different values. (3) The semiconductor integrated circuit device according to claim 2, wherein the first semiconductor region is a first well formed in the second semiconductor region. (4) The first semiconductor region is a second well formed in a third semiconductor region, and the second semiconductor region is a third well formed in the second well. , a semiconductor integrated circuit device according to claim 2. (5) The first semiconductor region is a fourth well formed in the fourth semiconductor region, and the second semiconductor region is a fifth well formed in the fourth semiconductor region. A semiconductor integrated circuit device according to claim 2.

Claims (5)

[Claims] (1) A first semiconductor substrate having a first substrate effect coefficient and a first main surface, and an LDD (lightly doped) formed on the first main surface of the first semiconductor substrate. a first transistor having a drain/source structure, and a second substrate effect coefficient different from the first substrate effect coefficient,
and a second semiconductor substrate having a second main surface;
and a second transistor having an LDD structure formed on the second main surface of the semiconductor substrate. (2) the first semiconductor substrate has a first substrate concentration;
The second semiconductor substrate has a second substrate concentration, and the first and second substrate effect coefficients have different values because the first substrate concentration and the second substrate concentration are different.
A semiconductor integrated circuit device according to claim 1. (3) The first semiconductor substrate is a first well formed in the second semiconductor substrate.
The semiconductor integrated circuit device described in . (4) The first semiconductor substrate is a second well formed in a third semiconductor substrate, and the second semiconductor substrate is a third well formed in the second well. ,
A semiconductor integrated circuit device according to claim 2. (5) The first semiconductor substrate is a fourth well formed in a fourth semiconductor substrate, and the second semiconductor substrate is a fifth well formed in the fourth semiconductor substrate. A semiconductor integrated circuit device according to claim 2.