JPH0199252A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a MOS transistor having a plurality of different threshold voltages by obtaining a plurality of well regions having different surface im purity concentrations by one ion implantation. CONSTITUTION:A well region 12 is formed by ion implanting into a silicon substrate 10. Then, a region in which its silicon face is exposed by thermal oxidizing in an oxygen atmosphere and a region of a silicon oxide film 14 are formed. Then, a low concentration well region 12a and a high concentration well region 12b are formed by heat treating in ammonia gas. Thereafter, a pad oxide film 18, and an antioxidation film 16, such as a nitride film, etc., are selectively formed. Subsequently, an element isolating insulating film 20 is formed by selectively oxidizing. Thereafter, a gate insulating film 22, a gate electrode 24 are formed, and source, drain 26 are formed at positions aligned to the electrode 24. Then, an intermediate insulating film 28 is formed on a whole surface, a contact window 29 is formed, and wiring metals 30 are further formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing MOS transistors having a plurality of different threshold voltages on the same silicon substrate.

[Prior art and its problems]

As a method for obtaining multiple threshold voltages in MOS transistors of the same conductivity type, for example, Japanese Patent Laid-Open No. 51-17681
There is channel doping by ion implantation as described in the above publication. This is achieved by using the fact that when the depth of the ion-implanted impurity distribution is sufficiently shallower than the surface depletion layer (and the impurity distribution can be approximated to a rectangle), the threshold voltage changes in proportion to the ion implantation amount. That is, one threshold voltage is obtained by controlling the impurity concentration on the silicon substrate surface.

Thereafter, for example, a resist or the like is formed over the entire surface, and an opening is formed using photorin technology in a region where the threshold voltage is to be changed. Furthermore, this opening is doped with an impurity of the same conductivity type or a different conductivity type as that of the silicon substrate.

However, when high-energy ion implantation is performed or when the impurity concentration is high to some extent, the change in the threshold voltage is no longer proportional to the ion-implanted bone of the channel dope, and the controllability of the threshold voltage deteriorates.

Therefore, there is a method of forming well regions having different surface impurity concentrations using ion implantation technology and photoetching technology, as described in, for example, Japanese Patent Application Laid-Open No. 54-100677. However, in the method described in JP-A-54-100677, in order to obtain two different threshold voltages, two photo-etching steps and two ion implantation steps are required to create wells with two different surface impurity concentrations. A MOS transistor is formed on this well region. Therefore, there is a problem that the manufacturing process is long and complicated.

[Object and structure of the invention]

It is an object of the present invention to solve the above problems and provide a method for manufacturing MOS transistors having different threshold voltages through a short and simple manufacturing process.

For this purpose, in the present invention, the surface of a well region formed by ion implantation forms a region where the silicon surface is exposed and a region where a silicon oxide film is formed.

After that, by performing heat treatment in ammonia gas,
A high concentration well region with a shallow impurity diffusion depth and a low concentration well region with a deep impurity diffusion depth are formed. Further, by forming MO8I-transistors on the low concentration and high concentration well regions, MOS transistors having different threshold 1 direct voltages are obtained.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1 showing a cross-sectional view of a MOS transistor.

First, a film such as a resist or a silicon oxide film to serve as a mask for ion implantation is formed over the entire surface of the silicon substrate 10. Thereafter, an opening is formed only in the well region using a photoetching technique, and a well region 12 is formed by ion implantation as shown in FIG. 1(a). This well region 12 can be formed of either the same conductivity type as the silicon substrate or a different conductivity type as long as it has an impurity concentration of 10'4 to 1015 cm-3. Thereafter, a silicon oxide film is formed on the entire surface by chemical vapor deposition (CCVD) or thermal oxidation in an oxygen atmosphere, and photoetching is performed to form a region where the silicon surface is exposed and a region where the silicon oxide film 14 remains.

After that, when heat treatment is performed in ammonia (CNH, ) gas, the region where the silicon surface is exposed becomes a high concentration well region 12 with a shallow impurity diffusion depth, as shown in FIG. 1 [b].
The region covered with the silicon oxide film becomes a low concentration well region 12a with a deep impurity diffusion depth. This is because the diffusion of impurities is promoted in the region covered by the silicon oxide film 14 due to the action of oxygen in the silicon oxide film, and the low concentration well region 12a
is formed. On the other hand, in the region where the silicon surface is exposed, ammonia gas and silicon react to form a thermal nitride film, suppressing the diffusion of impurities, and forming a high concentration well region 12b.

Note that the surface impurity concentration of this well region can be controlled by the thickness of the silicon oxide film, the heat treatment temperature and heat treatment time using ammonia gas.

Furthermore, by forming a nitride film on this silicon oxide film 14, a well region having a surface impurity concentration intermediate between that when there is a silicon oxide film on the well region and when the silicon surface is exposed can be obtained.

Thereafter, the silicon oxide film and the thermal nitride film formed by reacting ammonia gas with silicon are removed. After this, the pad oxide film 18. An oxidation-resistant film 16 such as a nitride film is selectively formed on the element region.

Next, as shown in FIG. 1C, selective oxidation is performed to form an element isolation insulating film 20. After that, the gate insulating film 22,
A gate electrode 24 is formed, and a source/drain 26 is formed at a position aligned with the gate electrode 24. Thereafter, an intermediate insulating film 28 is formed on the entire surface by the CVD method, a contact window 29 is formed, and a wiring metal 60 is further formed to form different thresholds on the low concentration well region 12a and the high concentration well region 12b. A MOS) transistor with a certain voltage can be obtained.

As an example, the results of manufacturing a P-channel MOS transistor using the manufacturing method of the present invention will be shown.

An ion implantation buffer film made of a silicon oxide film with a thickness of 1100 nm was formed on a silicon substrate with a surface orientation of 100 and a specific resistance of 10 to 20 Ω-cm.

Then acceleration energy 60keV, ion implantation amount 5X1
Phosphorous ion implantation was performed at 0''cm-2.

A region where a silicon oxide film with a thickness of 1100 nm is formed;
A region in which the silicon surface was exposed was provided on the ion implantation region, and heat treatment was performed in ammonia gas at a temperature of 1180° C. for 20 hours.

A P-channel MO8 transistor having a gate insulating film with a thickness of 8 Q nm was formed in these two well regions having different surface impurity concentrations. The threshold voltage of the MOS transistor in the well region where the silicon oxide film was formed is -0,
85V, M formed in the well region where the silicon surface is exposed
The OS transistor threshold voltage was -1.05V.

〔Effect of the invention〕

As is clear from the above description, well regions having a plurality of different surface impurity concentrations can be obtained by one ion implantation, and the manufacturing process of MOS transistors having a plurality of different threshold voltages can be shortened.

[Brief explanation of the drawing]

FIGS. 1(a), 1(b), and 1(c) are cross-sectional views showing the manufacturing process of a MOS transistor in one embodiment of the present invention. 12a...Low concentration well region, 12b...
...High concentration well region, 14...Silicon oxide film.

Claims (1)

[Claims] A step of introducing impurities into the silicon substrate by selectively implanting ions into the well region, a step of forming a silicon oxide film on the entire surface, and a step of photo-etching to remove the surface of the well region from the exposed silicon surface and the oxidized silicon substrate. a step of forming a region where the silicon film remains, and a step of forming a high concentration well region with a shallow impurity diffusion depth and a low concentration well region with a deep impurity diffusion depth by performing heat treatment in ammonia gas. , a step of forming an oxidation-resistant film on the element isolation region and performing selective oxidation, a step of forming a gate oxide film and a gate electrode, a step of forming a source/drain, a step of forming an intermediate insulating film, and a step of forming a contact. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of forming a window and forming a metal interconnect.