JPH0199341A - Fault detector - Google Patents

Abstract

PURPOSE:To attain fault detection of the device in on-line with less hardware quantity by utilizing the property that a signal is ciphered in a cryptographic device and then decoded resulting that the signal is restored to the original signal. CONSTITUTION:A 1st input signal is ciphered by a cryptographic means 4 in case of cryptographic processing and the result is outputted as the 1st output signal. In such a case, the 1st output signal is inputted as an input signal to a decoding means 5 via an input changeover means 6, the decoded output signal and the 1st input signal are compared by a comparator means 2 and when they are dissident, a device fault detection signal is outputted externally. In case of decoding, a 2nd input signal is inputted to the decoding means 5 via an input changeover means 6 and the result of decoding is outputted as the 2nd output signal. Since the cryptographic/decoding processing provided in advance are utilized as the function of the cryptographic device, the cryptographic device fault detector is realized with less hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Description of the technology to which the invention pertains The present invention relates to a failure detection device for a cryptographic device having an encryption processing function and a decryption processing function.

(2) Conventional technology [duplication] Conventionally, as shown in FIG. 4, nine processing means IA are duplicated.
, IB, these output signals A.

B is input to the comparing means 2, and when the output signals A and B do not match, the result is outputted to the outside of the apparatus by means of an apparatus failure detection signal. In the case of the processing means 1 in which the encryption means and the decryption means are configured separately, the encryption means and the decryption means each have a duplex configuration.

Furthermore, when the same processing means 1 performs encryption and decryption processing by switching, failure detection is performed while the connection relationship shown in FIG. 4 is maintained.

However, such duplication has the disadvantage that the device itself requires twice as much hardware.

Furthermore, when attempting to perform failure detection using some test patterns, even if duplication is used, there is a possibility that the difference in output signals will not be apparent.

Furthermore, if the device includes a sequential circuit part such as a register, even if a large number of test patterns are prepared, these test patterns will only be part of the input signals that can detect faults. Therefore.

There was a possibility that the fault would not be detected because it would not appear in the output signal.

[Use of expected value list]

Also, as shown in FIG. 5, based on a list 3 of combinations of input signals and expected value signals prepared in advance.

Comparing means 2 compares this expected value signal with the output signal of processing means 1.
A failure of the processing means is detected by comparing the values.

This configuration requires a large storage capacity because a combination of an input signal and an expected value signal or a signal 3 is prepared and held in advance for failure detection. Therefore, a method is adopted in which the test patterns used as input signals are limited to only a portion, but as a result, the probability of detecting a fault becomes low. Furthermore, it has the disadvantage that it is not possible to detect device failures online according to input signals during execution. Therefore, the fault detection rate was low and nine intermittent faults were not detected.

(3) Purpose of the Invention The present invention proposes a fault detection device for a cryptographic device that can detect faults in the device online with a small amount of hardware.

(4) Features of the Invention (4-1) Differences between Features of the Invention and the Prior Art In the prior art, normality was tested by comparing two items having the same expected value, but in the present invention.

By utilizing the property that the signal returns to its original state when the signal is encrypted and then decrypted in the encryption device, the normality is tested in one system.

In other words, if the encryption means and decryption means are normal, the input signal (plaintext) is encrypted, the output signal (ciphertext) is decrypted, and the result (decrypted plaintext) and the original input are Test to confirm that the signals (plaintext) match. Or vice versa.

Decrypts the input signal (ciphertext), encrypts the output signal (plaintext), and confirms that the output signal (re-encrypted ciphertext) matches the original input signal (ciphertext) Perform an inspection.

Therefore, since encryption and decryption which are provided in advance as functions of the cryptographic device are used, a fault detection device for the cryptographic device can be realized with less hardware.

(4-2) Description of Embodiment [First Embodiment] FIG. 1 shows the configuration of an embodiment corresponding to claim No. 11. In the figure, 2 is a comparison means, and 4 is an encryption means. , 5
6 represents a decoding means, and 6 represents an input switching means.

During encryption, the first input signal is encrypted by the encryption means 4, and the result is output as the first output signal. At this time, the first output signal is also input online as an input signal to the decoding means 5 via the input switching means 6, and the decoded output signal and the first input signal are inputted to the comparison means 2.
Compare by.

If they do not match, a device failure detection signal is output to the outside.

During decoding, the second input signal is input to the decoding means 5 via the input switching means 6, and the decoding result is output as a second output signal.

[Second Embodiment] The reference numerals in FIG. 0, which shows the configuration of an embodiment corresponding to the second recessed portion (2) of the patent claim, correspond to those in FIG.

At the time of decoding, the first input signal is decoded by the decoding means 5,
The result is output as a first output signal. At this time,
On-line, the first output signal is also input as an input signal to the encryption means 4 via the input switching means 6, and the encrypted output signal is inputted as an input signal to the encryption means 4.

The comparison means 2 compares the first input signal with the first input signal, and if they do not match, outputs a device failure detection signal to the outside.

During encryption, a second input signal is input to the encryption means 4 via the input switching means 6, and the encryption result is output as a second output signal.

[Third Embodiment] FIG. 3 shows the configuration of an embodiment corresponding to claim (3). Reference numeral 1 in FIG. 2 represents a comparison means, 6 represents an input switching means, 7 represents an input signal holding means, and 8 represents an output signal holding means.

In the case of encryption processing, the following processing is repeated (in the case of decryption processing, the processing is in parentheses).

■ Switch the mode of processing means 1 to encryption (decryption).

(2) Writing the input signal to the input signal holding means 7 and inputting it to the processing means 1 via the input switching means 6;

(2) Writing the output of the processing means 1 to the output signal holding means 8 and outputting it as an output signal.

■ Switch the mode of the processing means to decryption (encryption).

(2) Inputting the signal stored in the output signal holding means 8 to the processing means 1 via the input switching means 6.

(2) Inputting the output of the processing means 1 and the signal stored in the input signal holding means 7 to the comparison means 2;

■ Output the comparison result as a failure detection signal.

(5) Description of Effects As explained above, according to the present invention, only a small amount of parts need to be added to the main body of the encryption device. In other words, if the encryption means and the decryption means are of separate configurations, if the device failure detection device of claim 1 or 2 is adopted, a new part is added to the original encryption device. These are input switching means and comparison means.

This has the advantage that the present invention can be implemented with a small amount of hardware increment.

In addition, when switching between encryption and decryption in one processing means, if the device failure detection device according to claim (3) is adopted, the new part added to the original encryption device is the input The switching means, the input signal holding means, and the comparing means have the advantage that the present invention can be realized with a small hardware increase.

Further, according to the present invention, the failure detection rate is improved.

For example, in the case of a block cipher system that uses 64-bit blocks as units, if there is a 1-bit reversal failure of the input signal near the input of the encryption processing means, the encrypted output signal will correspond to the block unit. Since bit flips occur randomly over a wide range of 64 bits, disturbances cause changes throughout the output signal and are therefore easy to detect. Also, even if there is a 1-bit inversion failure in the output signal near the output of the encryption processing means.

This result is processed by the decoding processing means, and bit inversion occurs randomly over a wide range of 64 bits and is output, making it easier to detect failures.

[Brief explanation of the drawing]

Fig. 1 shows an example structure corresponding to claim No. +11, Fig. 2 shows an example structure corresponding to recessed portion (2) of the patent claim, and Fig. 3 corresponds to claim No. (3). Embodiment configuration, FIG. 4 is an example of a device failure detection device using duplication, and FIG.
The figure shows an example of a device fault detection device that uses an expected value list. In the figure, 1 is a processing means, 2 is a comparison means, 3 is an expected value list, 4 is an encryption means, 5 is a decryption means, 6 is an input switching means,
7 represents input signal holding means, and 8 represents output signal holding means. Patent applicant Nippon Telegraph and Telephone Corporation

Claims (3)

[Claims] (1) In an encryption device having an encryption means and a decryption means, an input switching means and a comparison means are provided, and a first input signal is input to the encryption means and the comparison means; a configuration for inputting an input signal to the input switching means; a configuration for inputting an output signal of the encryption means to the input switching unit and outputting it to the outside of the device as a first output signal; and an output signal of the input switching unit. an output signal of the decoding means is input to the comparison means and outputted to the outside of the device as a second output signal; and an output signal of the comparison means is used as a device fault detection signal to the device. What is claimed is: 1. A failure detection device that detects a device failure by having a configuration for outputting the output to the outside. (2) A cryptographic device having a decrypting means and an encrypting means, further comprising an input switching means and a comparing means, and inputting a first input signal to the decrypting means and the comparing means, and a second input signal. a configuration for inputting a signal to the input switching means; a configuration for inputting an output signal of the decoding means to the input switching means and outputting it to the outside of the apparatus as a first output signal; a configuration for inputting the signal to the encryption means; a configuration for inputting the output signal of the encryption means to the comparison means and outputting it to the outside of the apparatus as a second output signal; and an apparatus for using the output signal of the comparison means as a device failure detection signal. What is claimed is: 1. A failure detection device that detects a device failure by having a configuration for outputting the output to the outside. (3) A cryptographic device having a processing means for switching and executing encryption processing or decryption processing, comprising an input switching means, an input signal holding means, an output signal holding means, and a comparison means, and the input signal is transferred to the input signal holding means. and a structure for inputting the output signal of the processing means to the output signal holding means and the comparison means and outputting the output signal to the outside of the apparatus as an output signal; It is characterized by comprising a configuration for inputting the signal to the processing means and a configuration for inputting the output signal of the input signal holding means to the comparison means, and detects an apparatus failure by using the output signal of the comparison means as an apparatus failure detection signal. Fault detection device.