JPH02100535A - Non-instantaneous interruption line switch - Google Patents

Abstract

PURPOSE:To attain non-instantaneous interruption switch even when a transmission delay difference between a in-use/standby lines is large by adding a phase fluctuation suppression means to a non-instantaneous interruption line switch. CONSTITUTION:A clock signal generation circuit 11' includes a PLL circuit, and the noise band width is wide compared to that of a conventional example. Thus, the transmission delay difference between the in-use/standby lines is large. Even when the phase difference which occurs on switching the line, a clock phase synchronizing operation can be followed based on a phase control signal 115, and a phase synchronized clock signal 112 can be generated. Consequently, non-instantaneous interruption switch is attained even if the transmission delay difference of the in-use/standby lines is large.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to an uninterrupted line switching device in an uninterrupted line switching system for digital wireless communication, and particularly when the difference in transmission delay between working and protection lines is large. The present invention also relates to a no-interruption line switching device which can perform instantaneous interruption-less switching and also reduces the amount of phase fluctuation of a communication signal during line switching.

(Prior Art) Conventionally, in a digital wireless communication system, one backup circuit is provided for one or more working lines, and when a line fault occurs in the working line, the The communication signal being transmitted on the line is also sent one time on the protection line, that is, the same communication signal is transmitted in parallel on both the working line and the protection line, and at the receiving end, the faulty working line is transferred to the protection line instantly. Hitless switching (Hitles switching)
s5w1tch) to repair the faulty line.

The operation of uninterrupted line switching will be described below with reference to the drawings.

Figure 3 is a configuration diagram of the uninterrupted line switching system, showing an example in which the working line is N concave lines and the protection line is one line (N
is a natural number), 1 is a sending-end line switching controller that performs line switching control so that the communication signal of the faulty line is also transmitted on the protection line when a fault occurs in the working line, 2-1. ..., 2-N is a transmission end switch that connects the communication signal transmitted on the working line to the protection line, 3 is a pilot signal generator that generates a pilot signal to be transmitted on the protection line, and 4-0 is a Protection line multiplexer, 4-1. . . . , 4-N is a multiplexer for the working line; 5 is a receiving end line switching controller that controls switching between the working line and the protection line for the faulty line; 6-1, . . . , 6-
N is a line switching device that connects the working line and the protection line without any interruption, 7 is a pilot signal detector that detects the pilot signal transmitted on the protection line, and 8-0 is the line status of the protection line. Line monitor for monitoring 8-1. ..., 8
-N is a line monitor that monitors the line status of the working line, 9-
0 is a protection line separator, 9-1. . . , 9-N is a demultiplexer for the working line. In Figure 3, the working line (
The line switching operation will be explained by taking as an example a case where a line failure occurs in the line No. 1) and the line is switched to a protection line.

The line status of the working line (No. 1) is monitored by the line monitor 8-1, and a line monitoring signal 100-1 indicating the monitoring result is input to the receiving end line switching controller 5. When the line monitoring signal 100-1 indicates that a line fault has occurred, the receiving end line switching controller 5 uses the line monitoring signal +00-0 from the line monitor 8-0 of the protection line to detect the occurrence of a fault on the protection line. Check whether it is present. If there is no failure in the protection line, pilot signal detection signal 1 from pilot signal detector 7
01 to confirm the usage status of the protection line. When there is no failure in the working line and the protection line is not used for transmitting communication signals, the pilot signal +02 output from the pilot signal generator 3 is transmitted on the protection line.

Therefore, by detecting the pilot signal with the pilot signal detector 7 of the protection line, it is possible to know whether the protection line is unused.

If the protection line is not in use, the receiving end line switching controller 5 sends a sending end line switching instruction signal 103 to the sending end line switching controller.
Next, the sending-end line switching controller 1 outputs the sending-end switching control signal +04-1 to the sending-end switch 2-1 of the working line (No. 1) where the failure has occurred. Sending end switch 2
-1 is the input communication signal 1 so that the input communication signal 105 transmitted on the working line (No. 1) is also transmitted on the protection line.
Connect 05 to the backup line. That is, the sending end switch 2-
1 connects the line so that the input communication signal 105 is transmitted on both the working line (No. 1) and the protection line. Next, on the receiving end side, connect the working line (No. 1) where the fault has occurred.
The communication signal 106 received on the protection line and the communication signal 107 received on the protection line are input to the uninterrupted line switching device 6-1, and the receiving end switching control signal 109 from the receiving end line switching controller 5 -1, the communication signal 106 of the working line (No. 1)
The connection is switched from the communication signal 107 of the protection line to the output communication signal 1011, and the recovery of the faulty line is completed.

In the above-described uninterrupted line switching system, in order to perform line switching from a failure-occurring working line to a backup line without instant interruption, conventionally, an uninterrupted line switching device as described below is used. It is being

Figure 2 is a block diagram of a conventional uninterrupted line switching device, with 10
11 is a buffer memory circuit that temporarily stores and outputs the communication signal of the working line and the communication signal of the protection line, and 11 is a clock signal generation circuit that generates a clock signal whose phase is controlled based on the phase control signal from the buffer memory circuit 1o. , 12
is a switching circuit that switches between the working line communication signal and the protection line communication signal output from the buffer memory circuit 10 and outputs the communication signal. Communication signal transmitted over the working line +06
The communication signal +07 transmitted on the protection line is input to the buffer memory circuit 10.

Furthermore, a clock signal 110, a clock signal III, and a clock signal +12 are input to the buffer memory circuit 10. Clock signal 110 is a recovered clock signal of the working line system, and clock signal I11 is a recovered clock signal of the protection line system. Further, the clock signal +12 is the clock signal generated by the clock signal generation circuit 11, and the 0 communication signal +06 is the clock signal 110.
The communication signal +06 written and stored in the storage element of the buffer memory circuit 10 based on the clock signal 112
The working line communication signal +13 is read out from the storage element based on , and the working line communication signal +13 is output from the buffer memory circuit 10. The communication signal 107 is written to the storage element based on the clock signal Il+, the stored communication signal 107 is read out from the storage element based on the clock signal +12, and the backup line communication signal 114 is output from the buffer memory circuit 10. Ru. Further, the buffer memory circuit 10 switches and selects the clock signal +10 and the clock signal 11.1 based on the receiving end switching control signal 109, and performs phase comparison between the selected clock signal and the clock signal 112 to control the phase. Outputs signal 1!5.

The clock signal generation circuit 11 generates a clock signal whose phase is controlled based on the phase control signal +15! 12 is generated.

That is, the clock signal 112 is the receiving end switching control signal 10.
9 (clock signal 1
10 or clock signal l11).

Working line communication signal 11 output from buffer memory circuit 1o
3 and the protection line communication signal 114 are input to the switching circuit 12. The switching circuit 12 receives the receiving end switching control signal +09
Based on this, the working line communication signal +13 and the protection line communication signal 114 are switched and selected, and the output communication signal 108 is output. The above operation performs instantaneous switching.

In addition, if there is a transmission delay difference between the working line and the protection line, the communication signal +06 of the working line and the communication signal 10 of the protection line
7, and due to this phase difference, the output communication signal 10g has a phase fluctuation (phase jitter) at the time of line switching. Therefore, in order to suppress this amount of phase fluctuation to a predetermined value or less, P L L (
Clock phase synchronization is performed by extremely narrowing the noise bandwidth of the Phase Locked Loop (phase locked loop) circuit.

(Problem to be Solved by the Invention) However, in the conventional uninterrupted line switching device described above, in order to suppress the phase fluctuation amount at the time of line switching to a predetermined value or less, the noise bandwidth of the PLL of the clock signal generation circuit is is extremely narrow, so if the transmission delay difference between the working and protection lines is large, the phase difference that occurs when switching lines will be large, and the clock phase synchronization operation of the clock signal generation circuit will be difficult to deal with this large phase difference. There is a problem in that it is not possible to follow up and lose synchronization, making it impossible to switch without interruption.

An object of the present invention is to provide a clock signal including a PLL circuit with a noise bandwidth that enables clock phase synchronization even with a large phase difference, in order to solve the problems of the conventional uninterrupted line switching device. By having a generation circuit and a phase fluctuation suppression circuit for suppressing phase fluctuations after the switching circuit, it is possible to perform uninterrupted switching even when the transmission delay difference between the working and protection lines is large, and to reduce the amount of phase fluctuation. An object of the present invention is to provide an uninterrupted line switching device that outputs a communication signal in which the communication signal is suppressed to a predetermined value or less.

(Means for Solving the Problems) In order to achieve the above object, the present invention has the following means configuration.

That is, the uninterrupted line switching device of the present invention is capable of performing line switching between the working line and the protection line in a digital wireless communication uninterrupted line switching system having one protection line for one or more working lines. a clock signal generating means for generating a clock signal that is phase-synchronized with the clock signal of the working line system or the clock signal of the protection line system which is switched and selected based on the receiving end switching control signal to be controlled; a communication signal received on the working line; and the communication signal received on the protection line as input, stores the communication signal of the working line based on the clock signal of the working line system, and outputs the stored communication signal based on the clock signal output from the clock signal generating means. and storage means for storing a communication signal of a protection line based on a clock signal of the protection line system, and outputting the stored communication signal as a clock signal output from the clock signal generation means; a switching means that receives a communication signal of the working line and a communication signal of the protection line as input, and selects and outputs the communication signal of the working line or the communication signal of the protection line based on the receiving end switching control signal; an output of the switching means; The present invention is characterized by comprising: phase fluctuation suppressing means that receives a communication signal of and suppresses the amount of phase fluctuation of the communication signal to a predetermined value or less.

(for production) Next, the present invention configured as described above will be explained in detail.

The communication signal of the working line and the communication signal of the protection line inputted to the uninterrupted line switching device are inputted to the storage means. The communication signal of the working line is stored based on the clock signal of the working line system, and the communication signal of the protection line is stored based on the clock signal of the protection line system.

The stored communication signals of the working line and the communication signal of the protection line are output based on the black/y signal output from the clock signal generating means. The clock signal output from the clock signal generating means is phase-synchronized with the clock signal of the working line system or the clock signal of the protection line system. That is, the clock signal generating means generates either the clock signal of the working line system or the clock signal of the protection line system, which is selected for switching based on the receiving end switching control signal that controls line switching between the working line and the protection line. Generates a clock signal that is phase synchronized with the clock signal. The working line communication signal and the protection line communication signal output from the storage means are input to the switching means. The switching means is
Based on the receiving end switching control signal, either the input communication signal of the working line or the communication signal of the protection line is selected and output. The communication signal output from the switching means is input to the phase fluctuation suppressing means. The phase fluctuation suppressing means suppresses the phase fluctuation of the input communication signal and outputs a communication signal having an amount of phase fluctuation suppressed to a predetermined value or less. .

As a result of the above-described effects, even when the difference in transmission delay between the working line and the protection line is large, switching without interruption is possible, and a communication signal can be obtained in which the amount of phase fluctuation at the time of switching is less than or equal to a predetermined value.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an uninterrupted line switching device according to an embodiment of the present invention, in which 11' is a clock signal generation circuit, and 13 is a phase fluctuation suppression circuit. Further, the components assigned other numbers are the same as the components assigned the same numbers in the configuration diagram of the conventional uninterrupted line switching device shown in FIG. The difference between the embodiment of the present invention shown in FIG. 1 and the conventional example shown in FIG. The difference is that the width is different, and that a phase fluctuation suppression circuit 13 is added to the embodiment of the present invention. Therefore, in the following, the clock signal generation circuit 11' and the phase fluctuation suppression circuit 13
The operation will be explained, and explanations of other components similar to those of the conventional example will be omitted.

The clock signal generating circuit 11' of the embodiment of the present invention includes a PLL circuit, and its noise bandwidth is wider than that of the conventional example. In other words, even if the transmission delay difference between the working and protection lines is large and the phase difference that occurs when switching lines is large, the clock phase synchronization operation can follow based on the phase control signal 115, resulting in a phase-synchronized clock signal! +2 can be generated. Therefore, even if the difference in transmission delay between the working and protection lines is large, switching without interruption is possible.

Also, the output communication signal 1 (of the output of the switching circuit 12 at this time)
Although there are cases where H has a phase fluctuation amount greater than a predetermined value,
However, the output communication signal 108 is input to the phase fluctuation suppression circuit 13, and the output communication signal 108' suppressed to a phase fluctuation amount below a predetermined value is output from the phase fluctuation suppression circuit 13. The phase fluctuation suppression circuit 13 has a PLL circuit,
The noise bandwidth is set so that the amount of phase fluctuation can be suppressed to a predetermined value or less. When the transmission delay difference between the working and protection lines is large, the communication signal 106 of the working line and the communication signal 10 of the protection line input to the buffer memory circuit 10 are
Although the phase difference of 7 is large, the clock signal 112 output from the switching circuit 1
Since the phase fluctuation of the output communication signal 10g outputted after being switched in step 2 is reduced, the phase fluctuation suppression circuit 13 can suppress the amount of phase fluctuation to a predetermined value or less without causing synchronization loss.

(Effects of the Invention) As explained above, the present invention adds phase fluctuation suppression means to the conventional line switching device without momentary interruptions, so that even when the difference in transmission delay between the working and protection lines is large, there is no interruption. This has the advantage that it is possible to obtain a communication signal in which switching is possible and the amount of phase fluctuation at the time of line switching is suppressed to a predetermined value or less.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a line switching device without momentary interruption according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional line switching device without momentary interruption, and FIG. 3 is a block diagram of a line switching system without momentary interruption. . 1... Sending end line switching controller, 2-1 to 2-N
......Sending end switch, 3...Pilot signal generator, 4-0.4-1 to 4-N...Multiplexer, 5...・Receiving end line switching controller, 6-1
〜6-N・・・・・・No-interruption line switching device, 7・・・・
・Pilot signal detector, 8-0.8-1 to 8-N・
...Line monitor, 90.9-1~9-N...
...Separator, 10...Buffer memory circuit, 11.11'...Clock signal generation circuit, 12...Switching circuit, 13...
...Phase fluctuation suppression circuit, 100-0.100-1~!
00-N...Line monitoring signal, 101...
...Pilot signal detection signal, 102...
Pilot signal, lQ3... Sending end line switching instruction signal, +04-1 to 104-N... Sending end switching control signal, +05... Input communication signal, +06...
...Working line received communication signal, 107...
Protection line received communication signal, 108.108'...
・Output communication signal, 109.109-1 to +09-N...
...Receiving end switching control signal, 110...Working line system clock signal, Ill...Protection line system clock signal, 112...Clock signal, 11
3... Working line communication signal, +14...
- Reserve line communication signal, 115... Phase control signal. Agent: Yoshihiro Yahata, Patent Attorney
Figure 33

Claims (1)

[Claims] In a digital wireless communication uninterrupted line switching system having one protection line for one or more working lines, switching selection is performed based on a receiving end switching control signal that controls line switching between the working line and the protection line. clock signal generation means for generating a clock signal phase-synchronized with the clock signal of the working line system or the clock signal of the protection line system; The communication signal of the line is stored based on the clock signal of the working line system, the stored communication signal is outputted based on the clock signal output from the clock signal generating means, and the communication signal of the protection line is stored based on the clock signal of the working line system. storage means for storing the stored communication signal based on a clock signal of the system and outputting the stored communication signal as a clock signal output from the clock signal generation means; inputting the communication signal of the working line and the communication signal of the protection line output from the storage means; and a switching means for selectively outputting the communication signal of the working line or the communication signal of the protection line based on the receiving end switching control signal; the communication signal output from the switching means being input, and the phase fluctuation of the communication signal; phase fluctuation suppressing means for suppressing the amount to a predetermined value or less;
An uninterrupted line switching device characterized by comprising: