JPH02102734U - - Google Patents
Info
- Publication number
- JPH02102734U JPH02102734U JP1989011034U JP1103489U JPH02102734U JP H02102734 U JPH02102734 U JP H02102734U JP 1989011034 U JP1989011034 U JP 1989011034U JP 1103489 U JP1103489 U JP 1103489U JP H02102734 U JPH02102734 U JP H02102734U
- Authority
- JP
- Japan
- Prior art keywords
- resin
- sealed
- semiconductor chip
- leads
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の樹脂封止型半導体装置の第１
の実施例を示す断面図、第２図は本実施例装置に
用いられるリードフレームの形状を示す平面図、
第３図は本考案の第２の実施例を示す断面図、第
４図は本考案の第３の実施例を示す断面図、第５
図及び第７図は従来の樹脂封止型半導体装置を示
す断面図、第６図は従来半導体装置に用いられる
リードフレームの形状を示す平面図である。
１……リードフレーム、３……リード、５……
半導体チツプ、６……メツキ部、９……樹脂、１
０……チツプ接合部、１１……絶縁体。
Figure 1 shows the first example of the resin-sealed semiconductor device of the present invention.
FIG. 2 is a cross-sectional view showing an embodiment of the present invention; FIG. 2 is a plan view showing the shape of a lead frame used in the device of this embodiment;
FIG. 3 is a sectional view showing the second embodiment of the invention, FIG. 4 is a sectional view showing the third embodiment of the invention, and FIG. 5 is a sectional view showing the third embodiment of the invention.
7 and 7 are cross-sectional views showing a conventional resin-sealed semiconductor device, and FIG. 6 is a plan view showing the shape of a lead frame used in the conventional semiconductor device. 1...Lead frame, 3...Lead, 5...
Semiconductor chip, 6... Plating part, 9... Resin, 1
0...Chip joint, 11...Insulator.
Claims (1)
と各電極に対応した複数のリードとを有し、複数
のリードの端部に対応する電極が直接接合される
と共にこれら接合部を含む半導体チツプが樹脂封
止されたことを特徴とする樹脂封止型半導体装置
。 The semiconductor chip has a plurality of electrodes formed on the periphery and a plurality of leads corresponding to each electrode, and the electrodes corresponding to the ends of the plurality of leads are directly bonded, and the semiconductor chip including these bonded parts is A resin-sealed semiconductor device characterized by being resin-sealed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989011034U JPH02102734U (en) | 1989-02-01 | 1989-02-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989011034U JPH02102734U (en) | 1989-02-01 | 1989-02-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02102734U true JPH02102734U (en) | 1990-08-15 |
Family
ID=31219230
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989011034U Pending JPH02102734U (en) | 1989-02-01 | 1989-02-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02102734U (en) |
-
1989
- 1989-02-01 JP JP1989011034U patent/JPH02102734U/ja active Pending