JPH02102734U - - Google Patents

Info

Publication number
JPH02102734U
JPH02102734U JP1989011034U JP1103489U JPH02102734U JP H02102734 U JPH02102734 U JP H02102734U JP 1989011034 U JP1989011034 U JP 1989011034U JP 1103489 U JP1103489 U JP 1103489U JP H02102734 U JPH02102734 U JP H02102734U
Authority
JP
Japan
Prior art keywords
resin
sealed
semiconductor chip
leads
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989011034U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989011034U priority Critical patent/JPH02102734U/ja
Publication of JPH02102734U publication Critical patent/JPH02102734U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図は本考案の樹脂封止型半導体装置の第１
の実施例を示す断面図、第２図は本実施例装置に
用いられるリードフレームの形状を示す平面図、
第３図は本考案の第２の実施例を示す断面図、第
４図は本考案の第３の実施例を示す断面図、第５
図及び第７図は従来の樹脂封止型半導体装置を示
す断面図、第６図は従来半導体装置に用いられる
リードフレームの形状を示す平面図である。 １……リードフレーム、３……リード、５……
半導体チツプ、６……メツキ部、９……樹脂、１
０……チツプ接合部、１１……絶縁体。

Claims (1)

    【実用新案登録請求の範囲】
  1. 周辺部に複数の電極が形成された半導体チツプ
    と各電極に対応した複数のリードとを有し、複数
    のリードの端部に対応する電極が直接接合される
    と共にこれら接合部を含む半導体チツプが樹脂封
    止されたことを特徴とする樹脂封止型半導体装置
    。
JP1989011034U 1989-02-01 1989-02-01 Pending JPH02102734U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989011034U JPH02102734U (ja) 1989-02-01 1989-02-01

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989011034U JPH02102734U (ja) 1989-02-01 1989-02-01

Publications (1)

Publication Number Publication Date
JPH02102734U true JPH02102734U (ja) 1990-08-15

Family

ID=31219230

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989011034U Pending JPH02102734U (ja) 1989-02-01 1989-02-01

Country Status (1)

Country Link
JP (1) JPH02102734U (ja)

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