JPH0210456A - I/o address allocating method - Google Patents

Abstract

PURPOSE:To relax restrictions on circuit design by dividing an I/O address space by the number of slots, which can be mounted, to allocate a wide address space to each mounting option device. CONSTITUTION:When an option board 1 is stored in a slot of a storage means to which a slot discrimination signal is supplied, a board selecting circuit 2 of the option board 1 discriminates whether the circuit 2 itself is selected or not based on the slot discrimination signal and an address signal which are inputted through pins, and the circuit 2 outputs an acknowledge signal to a device number output circuit 4 when discriminating that the circuit 2 itself is selected. The device number output circuit 4 outputs a data signal indicating the device number peculiar to the circuit itself to the storage means based on the acknowledge signal and the slot discrimination signal. The I/O address space is allocated to option devices of two option boards 1 by the number of slots provided for storage of option boards 1.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to an I/O address allocation method for allocating an address space for an optional device of a word processor or the like.

<Prior Art> Conventionally, word processors have been equipped with various optional boards, such as additional kana-kanji conversion dictionary memory, and these optional boards have been equipped with multiple slots of a mother port provided as a means of accommodating the word processor. It is inserted into the 7th port and connected. Then, the CPU of the word processor allocates I/O address spaces to the devices of the option boards arranged in these slots in the following manner.

For example, the I/O address space for optional devices is 16K 13 from 8000o to BFF'FH, and the total number of optional devices (optional boards) is 16.
, CI) U is the number of addresses to be allocated to each optional device as 16KB/I6=IKI3
As, device l has 8000H to 83F F u ,
Three IKF addresses are sequentially assigned to device 2, such as 8' 400 o to 87 F F H device numbers r3cOOH-BFFFo.

<Problems to be Solved by the Invention> However, in the conventional word processor 1/O address allocation method described above, each option is allocated by the number of addresses obtained by simply dividing the entire I/O address space by the total number of optional devices. Since addresses are allocated to devices, there is a drawback that as the number of optional devices increases, the number of addresses allocated per I-device uniformly decreases regardless of the number of optional devices installed. In other words, in Moe's example, there are only four slots that can be installed on the motherboard, and one device has 16KB.
/4 = Even though addresses can be allocated in increments of 4KB, the total number of optional devices is 1.
6, it has the disadvantage that only one IKB can be allocated per device. In addition, the number of addresses required by each optional device varies in size and is not necessarily known, so the uniform address allocation method based on the total number of devices as described above imposes scale restrictions on the optional device side and It has the disadvantage of limiting the circuit design of the processor.

Therefore, an object of the present invention is to divide the I/O address space not by the total number of optional devices but by the number of slots that can be installed, thereby making it possible to allocate a wide address to each installed optional device, thereby limiting the size of optional devices. It is an object of the present invention to provide a method for allocating addresses (1)/O, which can alleviate restrictions on the circuit design of main electronic equipment.

<Means for Solving the Problems> In order to achieve the object described in -, the I/O address allocation method of the present invention includes a digital slot identification signal representing a slot number in the slot of the accommodation means for accommodating the option board. Provide the supplied pins on the optional board,
A selection determination means for determining whether or not one is selected based on the slot identification signal and address signal inputted via the above pin, and a In the I/O address allocation device, the I/O address allocation device is equipped with a device number output means for outputting a data signal representing a device number.
The feature is that an address space is allocated to each optional device.

<Operation> Now, for example, four slots are provided in the storage means, one
~For example, set “0” to the lower two pins of the 4th slot.
It is assumed that slot identification signals of 0'', 0bi, ``/O'', and ``Ibi'' are supplied.For example, suppose that option boards are accommodated in slots 1 and 2, respectively.Then, each of the above The selection determination means of the obunyong board determines whether or not it has been selected based on the slot identification signal and address signal input via the pin, and when it determines that it has been selected, it sends an affirmative signal to the device number output means. The device number output means outputs a data signal representing its own unique device number to the accommodating means based on the affirmative signal and the slot identification signal ("00", "0bi"). Then, the I/O address space is allocated to the optional devices of the two optional boards according to the number of slots (4) provided for accommodating the optional boards. In this way, the I/O address space becomes, for example, 16
In the case of KB, in the two-layer example, addresses of 16 KB/4=4 KB are allocated to two optional devices accommodated in slots 1 and 2. Therefore, when the total number of optional devices is 16 as in the past, we do not uniformly allocate IKB addresses to each device, but instead allocate the entire I/○ address space depending on the number of slots. Can be secured and I/O
Make effective use of address space.

<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

FIG. 1 shows identification signals of four slots provided on a motherboard (not shown), which serves as a housing means that constitutes one of the I/O address allocation devices of the present invention. That is, each slot has a predetermined number of pins for signal line connection,
The option board that forms the other side of the I/O address allocation device is inserted and fixed, but among the predetermined number of pins mentioned above, pins 0 and 1, SLO and SLI, are connected to GND as shown in Figure 1.
Alternatively, it is connected to +5V to output a digital slot identification signal representing the slot number.

On the other hand, FIG. 2 is a schematic block diagram of an option board inserted and fixed in the slot, and this option board l is selected based on the address signal input through the slot and the slot identification signal. a board selection circuit 2 as a selection determining means for determining whether or not the board selection circuit 2 has been selected; an I/O address decoder 3 that transmits an affirmative signal from the board selection circuit 2 and decodes the address signal; It consists of a device number output circuit 4 that outputs a data signal representing a device number specific to the option board based on the output signal. Further, the CPU (not shown) on the motherboard side allocates an I/O address space as described later according to the number of slots provided for accommodating the option board, that is, four.

FIG. 3 shows a specific example of an option board in which the total I/O address space of the option device is 16KI3 from 80008 to BF F F H, and four slots are provided in the mother port. In the same figure, address line Δ1
Among 5 to AO, (Al5.Al4) always has (1,0
) is input, the slot identification signal (SLI, 5LO) in Figure 1 is input to (A I 3.A I 2), and (
An address signal that specifies the address of each optional device is input to (All, . . . , AO). The board selection circuit 2 receives signals (1,
Decoder II to which 0) is input, and E to which signals from slot No. 1 pin SLI and address line △13 are input.
It consists of an XOR element I2, an EXOR element 13 to which signals from pin 0 of the slot SLO and address line A12 are input, and a NAND element 14 which takes the sum of their inverted outputs. When the same signal as the identification signal (SLI, 5LO) is input to A13 and Al2, it outputs a board selection signal which is an affirmative signal indicating that it has been selected.

The I/O address decoder 3 receives the board selection signal, decodes the address data input to the address lines AO to All, and outputs an address designation signal to that address on the option board. A signal is output to the buffer 15 as the device number output circuit 4, and the buffer 15 that receives this output signal outputs a data signal (OPO to ○P3) as shown in FIG. 4 representing the device number specific to the option board. is output to data lines DO to D3.

The operation of the I/O address allocation device having the above configuration will now be described with reference to FIG.

Now, for example, slots 1 and 2 shown in FIG.
Assume that the No. 2 option board is inserted. Then, the board selection circuit 2 of the No. 1 option board is
A slot identification signal (SL
I, 5LO=0. The same signal as O) is sent to address lines A12~
When input to AI5 (Al2.A13.A14.A
15=0.0.0■), outputs the board selection signal to the I/O address decoder 3, and then outputs the board selection signal to the I/O address decoder 3.
deciphers the address data AO to All and outputs an addressing signal to that address on the option board, and then outputs a signal to the buffer 15. Then, buffer 1
5 transmits a data signal (0, 0, 0, 0) representing the device number (1) of the option board to data lines DO to D3.
Output to the mother port side via. Similarly, the second option board outputs a data signal (0, 0, 0, 1) representing its own device number (2) to the motherboard side.

On the other hand, the CPU (not shown) on the motherboard side first reads address 8000 in the I/O address space and reads the device number (o, o, o, o) of the option board in the first slot.
is read from D3 to Do, and the I/O address is 8.
Arrange from address 001.

Next, read address 9000, read out the device number (0, 0, 0, 1) of the option board in the second slot in the same way, and place the I/O address from address 9001. Even if the Otsu Obso Yon board is inserted into the 3rd and 4th slots, the I/O addresses thereof are similarly arranged starting from address 001 and address BOO1. Thus, if the total 1/O address space is 16KB, this can be divided into 4 slots.
An address of 4 KB is assigned to each option board device.

Therefore, the total number of optional devices is 16 as before.
(See Figure 4), instead of allocating IKB addresses uniformly to each device, the entire 1/O address space is allocated to the number of slots, that is, the number of devices that can be installed at the same time. A large number of addresses can be secured per unit, and restrictions regarding the memory size of optional devices and restrictions regarding circuit design on the mother port side can be significantly relaxed, and I/O addresses can be effectively utilized. Further, in the above embodiment, since the substrate selection circuit 2 is configured as shown in FIG. 3, an ink clock can be applied to the input signal using the EXOR elements 12, 13, etc., thereby preventing erroneous output.

In the above embodiment, the number of slots is 4, and 1.2
The number of slots in the motherboard 1 can be arbitrarily selected as described above for the case where option boards numbered 1 and 2 are inserted into slots numbered 1 and 2, respectively. Also, no matter which numbered option board is inserted into which numbered slot, each option board (all 1/O address space/
The I/O address space is automatically allocated according to the number of slots).

It goes without saying that the present invention is not limited to the two-legged embodiment.

<Effects of the Invention> As is clear from the following explanation, the I/O address allocation method of the present invention has the advantage of assigning a pin to which a slot identification signal is supplied to a slot of an accommodating means for accommodating an option board. On the other hand, the selection determination means of the obunyong board determines whether or not it has been selected based on the slot identification signal and address signal input through the pin, and when it determines that it has been selected, it outputs the device number. The means outputs a data signal representing a unique device number, and the CPU of the accommodating means allocates an I/O address space to each optional device according to the number of slots provided for accommodating the optional board. As a result, a large I/O address space can be allocated to each optional device, and more addresses can be secured per device than in the conventional case where addresses were allocated uniformly depending on the total number of devices. , restrictions on the scale of optional devices and restrictions on circuit design of equipment on the accommodating means side can be significantly relaxed, and I/O address space can be used effectively.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing identification signals of slots of a housing means that constitutes one side of the I/O address allocation device of the present invention, and FIG. 2 is a schematic block diagram of an option board that forms the other side of the above-mentioned I/O address allocation device. FIG. 3 is a diagram showing a specific example of the option board, and FIG. 4 is a diagram showing a data signal output from the option board. L・Option board, 2... Board selection circuit, 3・I
/O address decoder, 4...Device number output circuit.

Claims (1)

[Claims] (1) A pin to which a digital slot identification signal representing the slot number is supplied is provided in the slot of the accommodation means, and the option board is selected based on the slot identification signal and address signal input via the pin. and a device number output means for outputting a data signal representing a device number specific to the option board based on an affirmative signal from the selection determining means. 1. An I/O address allocation method, characterized in that, in an allocation device, an I/O address space is allocated to each option device according to the number of slots provided for accommodating option boards.