JPH02105272U - - Google Patents
Info
- Publication number
- JPH02105272U JPH02105272U JP1054189U JP1054189U JPH02105272U JP H02105272 U JPH02105272 U JP H02105272U JP 1054189 U JP1054189 U JP 1054189U JP 1054189 U JP1054189 U JP 1054189U JP H02105272 U JPH02105272 U JP H02105272U
- Authority
- JP
- Japan
- Prior art keywords
- data
- type memory
- fifo type
- circuit
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000006870 function Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 1
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
Description
第１図は本考案になるデジタル同期回路の一実
施例を示す構成図、第２図は変形例を示す図、第
３図は従来例を示す図、第４図はデジタルデータ
再生装置の一般的な構成を示す図である。
２０……ＦＩＦＯ型メモリ、２１……固定クロ
ツク、２２……マスク回路、２３……デコーダ、
２４……積分器、２５……ＶＣＸＯ、２６……分
周器。
Fig. 1 is a block diagram showing an embodiment of the digital synchronous circuit according to the present invention, Fig. 2 is a diagram showing a modified example, Fig. 3 is a diagram showing a conventional example, and Fig. 4 is a general diagram of a digital data reproducing device. FIG. 20... FIFO type memory, 21... Fixed clock, 22... Mask circuit, 23... Decoder,
24... Integrator, 25... VCXO, 26... Frequency divider.
Claims (1)
するＦＩＦＯ型メモリと、前記ＦＩＦＯ型メモリ
に供給されたデータを断続的に書き込むデータ書
き込みパルス生成回路と、前記ＦＩＦＯ型メモリ
からデータを連続的に読み出すデータ読み出しパ
ルス生成回路とからなるメモリ回路であつて、 前記ＦＩＦＯ型メモリに書き込まれたデータ容
量の変化に応じて、前記ＦＩＦＯ型メモリからの
データ読み出し速度を変化させる手段を設けたこ
とを特徴とするデジタルデータ同期回路。[Claims for Utility Model Registration] A FIFO type memory having a flag function indicating the amount of written data, a data write pulse generation circuit for intermittently writing data supplied to the FIFO type memory, and a data write pulse generation circuit for intermittently writing data supplied to the FIFO type memory; A memory circuit comprising a data read pulse generation circuit for continuously reading data, the memory circuit comprising means for changing the data read speed from the FIFO type memory in accordance with a change in the data capacity written in the FIFO type memory. A digital data synchronization circuit characterized in that it is provided with a digital data synchronization circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1054189U JPH02105272U (en) | 1989-01-31 | 1989-01-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1054189U JPH02105272U (en) | 1989-01-31 | 1989-01-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02105272U true JPH02105272U (en) | 1990-08-21 |
Family
ID=31218294
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1054189U Pending JPH02105272U (en) | 1989-01-31 | 1989-01-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02105272U (en) |
-
1989
- 1989-01-31 JP JP1054189U patent/JPH02105272U/ja active Pending
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