JPH0210539B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a latching relay drive circuit,
In particular, it relates to a latching relay drive circuit that operates a latching relay by driving a semiconductor switching circuit in response to signals from an input terminal and an auto-reset or auto-set terminal for controlling the operation of the latching relay. The main object is to provide a latching relay drive circuit which eliminates noise in signals from each input terminal with a simple configuration and prevents malfunctions.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an overall circuit diagram of an embodiment of the present invention. The logic circuit 1 is connected to a reset input terminal R, a set input terminal S, a toggle input terminal T, and a monostable input terminal M via input interface circuits 2, 3, 4, and 5, respectively. R, S, T, and M are connected to external transistor-transistor-logic circuits (TTL).
A signal from a complementary metal oxide semiconductor (C-MOS) or the like is inputted without using a buffer or the like. An auto-reset or auto-set terminal A is connected to the logic circuit 1, and from this auto-reset or auto-set terminal A, the initial state of the relay switch 6 is determined when the power is initially turned on or when the power is restored after a momentary power outage. A signal is given to detect the From the logic circuit 1, each terminal R,
In response to input signals from S, T, M, and A, signals for operating the semiconductor switching circuit 7 are derived. The semiconductor switching circuit 7 includes a so-called one-winding latching relay 8. Further, a monostable circuit 9 and a constant voltage circuit 10 are connected to the logic circuit 1. Note that the logic circuit 1 operates when a negative logic signal, that is, a signal that is normally at a high level becomes a low level, as an operation signal.

When a reset signal is input from the reset terminal R, the latching relay 8 is reset if it is in the set state, and the reset state is maintained if it is in the reset state. When the set signal from the set terminal S is input, the set state is maintained when the latching relay 8 is in the set state, and it is brought into the set state when it is in the reset state. Further, when a toggle signal from the toggle terminal T is input, the latching relay 8 is alternately inverted between a set state and a reset state in accordance with changes in the pulse of the toggle signal. Furthermore, when a monostable signal is input from the monostable terminal M, the latching relay 8 repeats the reset state and the set state in response to the rise and fall of the monostable signal.

In the semiconductor switching circuit 7, the diode 11 and the transistors TR1 and TR2 are connected in series, and the connection point 12 between the transistors TR1 and TR2
is connected to one terminal of the relay coil 13.
The diode 14 and the transistors TR3 and TR4 are connected in series, and a connection point 15 between the transistors TR3 and TR4 is connected to the other terminal of the relay coil 13. A relay coil 13 is connected between connection points 12 and 15.
A Zener diode 16 is used to prevent back electromotive force.
17 are connected in opposite directions.

The output of AND gate G1 is transistor TR5
and the base of the aforementioned transistor TR2. transistor
The collector of TR5 is connected to the base of transistor TR6. The output of AND gate G2 is applied to the base of transistor TR4 and also to the base of transistor TR7. The collector of transistor TR7 is connected to the base of transistor TR8.

When the set signal from AND gate G1 is applied to the bases of transistors TR2 and TR5, transistors TR3 and TR2 become conductive, and excitation current flows through relay coil 13 in the direction of arrow 18, setting latching relay 8. . On the other hand, the reset signal from AND gate G2 is applied to transistor TR.
When applied to the bases of transistors TR1 and TR4, the excitation current flows through the relay coil 13 in the direction of the arrow 19 opposite to the arrow 18, and the latching relay 8 is reset.

Zener diodes 16 and 17 are relay coil 1
Absorbs the back electromotive force due to the inductance of No. 3.
The Zener voltage Vz of these Zener diodes 16 and 17 must satisfy the following conditions. First, (1) when the supply voltage Vcc supplied to the terminal 20 reaches the maximum, the Zener diodes 16 and 17 do not conduct due to the voltage applied to the relay coil 13. That is, if the zener voltage Vz is lower than the voltage applied to the relay coil 13, the zener diodes 16 and 17 become conductive, and the excitation current no longer flows through the relay coil 13, causing the latching relay 8 to become inoperable. Next (2) Zener voltage Vz
is lower than the minimum breakdown voltage section of the semiconductor switching circuit 7. In other words, in order for the back electromotive force generated across the relay coil 13 to be absorbed by the Zener diodes 16 and 17, the Zener voltage must be
Vz must be set lower than the minimum breakdown voltage section of the semiconductor switching circuit 7. The conditions (1) and (2) above are summarized as follows.

VR<Vz<Vm (1) In the first equation, the symbol VR is the voltage applied to both ends of the relay coil 13 when the supply voltage Vcc is maximum, and the symbol Vm is the minimum breakdown voltage of the semiconductor switching circuit 7.

By the way, in the conventional semiconductor switching circuit, the diodes 11 and 14 are not provided, so when the supply voltage Vcc is in the range of 4.75 to 15V, the first
cannot satisfy the formula. That is, Vcc=
When the voltage is 15V, the voltage applied to both ends of the relay coil 13 is 10V. Here, the Zener diode 16,
The voltage of 17 is about 7.4V per piece because the reverse breakdown voltage between the base and emitter is used, and since two pieces are connected in series, the total voltage is about 14.8V.
However, the minimum breakdown voltage of the semiconductor switching circuit 7
Vm is the sum of the reverse breakdown voltage between the base and emitter of the transistors TR3 and TR1 and the minimum value of the supply voltage Vcc, and is approximately 12.15V. Therefore, the first equation cannot be satisfied. Therefore, in conventional semiconductor switching circuits, the Zener diode 1
6 and 17 are provided, but the relay coil 1
This means that the back electromotive voltage of No. 3 was not absorbed by the Zener diodes 16 and 17 and was leaked to the terminal 20.
However, according to this embodiment, the diodes 11 and 14 are provided in the minimum breakdown voltage section of the semiconductor switching circuit 7.
Therefore, the minimum withstand voltage Vm is the sum of the reverse withstand voltage between the emitters and bases of transistors TR3 and TR1, the reverse withstand voltage between the emitters and bases of diodes 11 and 14, and the minimum value of the supply voltage Vcc. , for example, 7.4+7.4+4.75=19.55V. Therefore, the first equation can be satisfied, and the back electromotive force of the relay coil 13 is equal to that of the Zener diode 1.
6, 17 will definitely be absorbed.

Referring to FIG. 2, in the input interface circuit 2, the reset input terminal R is connected to the transistors via diodes 21, 22, 23, and 24.
connected to the base of TR9, transistor TR9
The collector of is connected to the reset input priority circuit 25. The diode 22 is a collector-base diode of a transistor, and has a reverse breakdown voltage of 70 to 100V. This diode 22 suppresses surges from the transmission line. Note that a terminal 26 for supplying voltage from the constant voltage circuit 10 is connected between the diodes 22 and 23. The other input interface circuits 3, 4, and 5 are configured similarly to the above-mentioned interface circuit 2, and the output of the interface circuit 3 is given to the reset input priority circuit 25, and the output of the interface circuit 3 is given to the reset input priority circuit 25. The output is given to a toggle input priority circuit 27.

The reset input priority circuit 25 receives a reset signal inputted from the reset input terminal R via the input interface circuit 2 and a set signal inputted from the set input terminal S via the input interface circuit 3 at the same time. This is a circuit that gives priority to the reset signal and supplies it to the next first noise removal circuit 28 when the noise is removed. Also, the toggle input priority circuit 27
is a toggle signal when a toggle signal input from the toggle input terminal T via the interface circuit 4 and a monostable signal input from the monostable input terminal M via the interface circuit 5 are input simultaneously. This circuit gives priority to the signal and supplies it to the first noise removal circuit 28. Note that when the reset signal and the toggle signal are input at the same time, the reset signal is given priority in the flip-flop 29 at the subsequent stage. Therefore, logic circuit 1
In this case, the overall signal priority is reset signal>set signal>toggle signal>monostable signal.

The first noise removal circuit 28 removes negative direction noise that has arrived on the signal line. Here, negative direction noise is the noise represented by N ^- in Figure 3, and is noise that causes the input signal to be at a low level when the input signal is at a high level, that is, when no operating signal is given. It is. Further, the positive direction noise is the noise represented as N ⁺ in FIG. Note that the first noise removal circuit 28 includes:
Each signal is inverted and provided, so in the first noise removal circuit 28, the negative direction noise N ^- is at a high level and the positive direction noise N ⁺ is at a low level.

In the first noise removal circuit 28, the reset signal via the reset input priority circuit 25 is connected to line 3.
0 to OR gate G3 through
The set signal is applied to one input of AND gate G4, and the set signal is applied via line 31 to OR gate G3 and to one input of AND gate G5. Also, the toggle input priority circuit 27
The toggle signal via line 32 is applied to OR gate G3 and AND gate G6.
The monostable signal is applied via line 33 to OR gate G3 and to one input of AND gate G7. The output of OR gate G3 is the delay circuit 3
4 through AND gates G4, G5, G6, G7
are respectively applied to the other input terminals of the . According to the first noise removal circuit 28, the delay circuit 3
All signals with a pulse width shorter than the delay time in step 4, that is, noise, are removed. Note that circuits that remove noise using delay circuits and AND gates are well known, but according to the first noise removal circuit 28 of the present invention, noise on four signal lines can be removed by just providing one delay circuit 34. It can be removed and the circuit configuration is simple.

The output of AND gate G6 is applied to a second noise removal circuit 35 shown in FIG. In the second noise removal circuit 35, the output of the AND gate G6 is given to the inverting circuit 36, and the output of the inverting circuit 36 is outputted via the delay circuit 37 and the line 3
8 and the delay circuit 37 is wired and connected to line 38. According to the second noise removal circuit 35, positive direction noise N ⁺ in negative logic is removed. The output of the AND gate G7 is given to a third noise removal circuit 39 configured similarly to the second noise removal circuit 35, and this third noise removal circuit 39 also removes positive direction noise N ⁺ in negative logic. Ru. An output line 42 of the third noise removal circuit 39 is connected to an edge detector circuit 43. This edge detector circuit 4
3 generates one pulse in response to the rise or fall of the input signal, and the output of the edge detector circuit 43 is connected to one input terminal of the AND gate G8 via the OR gate G13 in the middle of the line 44. A line 38 is connected to one input terminal of the OR gate G13.

The output of AND gate G4 is flip-flop 2
9's clear terminal CLR, AND gate G
The output of 5 is connected to the preset terminal PRS of flip-flop 29. In this way, the reset signal and the set signal are applied to the flip-flop 29 only after the negative direction noise N ^- is removed by the first noise removal circuit 28, but this is because the flip-flop 29 is set or reset. This is because the setting or resetting is simply repeated many times due to the positive direction noise N ⁺ , and the operation is not affected.

Auto-reset or auto-set terminal A
is connected to the base of transistor TR10 via a line 46 comprising a diode 45. The collector of the transistor TR10 is connected to an inverting circuit 47, and the output of the inverting circuit 47 is connected via a line 48 to an output line 49 of an AND gate G5 by an OR gate G14, and also to an inverting circuit 50. The output of this inversion circuit 50 is line 5
1 to the output line 52 of AND gate G4.
and is connected by OR gate G15. line 48,
In the middle of line 51, the output of inverting circuit 53 is connected to line 11.
1,112. The inverting circuit 53 is supplied with the output of the inverting circuit 54, and the inverting circuit 54 includes a transistor TR.
11 collectors are connected. this transistor
A terminal 59 is connected to the base of the TR11 via diodes 55, 56, a capacitor 57, and a resistor 58 for increasing the delay time.
A voltage from the constant voltage circuit 10 is supplied to the terminal 59 . The output of the inverting circuit 54 is wired and connected to the output line 60 of the inverting circuit 53 via a line 110, and the line 60 is connected to one input terminal of an OR gate G12.

Note that there is a terminal 6 in the middle of the line 46 for applying voltage from the constant voltage circuit 10 via a resistor 62.
3 is connected, one end of the relay switch 6 is connected, and the other end of the relay switch 6 is grounded.

Such a circuit determines the initial state of the latching relay 8 upon initial power-up or upon recovery from a momentary power failure. That is, when the relay switch 6 is in the conductive state, it becomes an auto-set circuit, and if the previous state of the latching relay 8 is reset when the power is turned on, it becomes the set state, and if the previous state of the latching relay 8 is the set state. If so, the latching relay 8 remains as it is. Also, when the relay switch 6 is cut off, it becomes an auto-reset circuit, and if the previous state of the latching relay 8 is set when the power is turned on, it becomes the reset state, and if it is in the reset state, the latching relay 8 maintains the reset state. . Therefore, if the relay switch 6 of the latching relay 8 is connected as shown in FIG. 1, the latching relay 8 will maintain its previous state when the power is turned on.

To explain the operation with reference to Fig. 5, Fig. 5 1
When the power is turned on as shown in FIG. 5, the constant voltage circuit 10 is activated at a certain voltage value as shown in FIG. 2. In response to the activation of this constant voltage circuit 10, the resistor 5
The capacitor 57 starts charging via the diode 55,
When it becomes equal to the sum of the forward voltage drop of 56 and the voltage between the base and emitter of transistor TR11,
TR11 becomes conductive and the collector voltage becomes low level. Correspondingly, the output of the inverting circuit 54 becomes high level, and the output of the inverting circuit 53 becomes low level as shown in FIG. 5. On the other hand, when the constant voltage circuit 10 is activated in a state where the relay switch 6 is cut off, for example, the transistor TR1
0 becomes conductive, and accordingly, the output of the inverting circuit 47 becomes high level as shown in FIG. In addition,
When relay switch 6 is conductive, transistor TR10 is cut off and the output is at high level, so the output of inverting circuit 47 is at low level. In response to the output of the inversion circuit 47 becoming high level, the output of the inversion circuit 50 becomes the fifth level.
As shown in FIG. 5, it becomes a low level.

Line 48 includes an inverting circuit 47 and an inverting circuit 53.
Since the output of the line 48 is wired and derived, the signal derived on the line 48 is as shown in FIG. The signal on this line 48 is at a high level only while the output of the inverting circuit 53 is at a high level, that is, while the capacitor 57 is being charged to the final charging voltage. It will be reset. During this time, the signal led out to line 51 remains at a low level as shown in FIG. 5. In addition, when the relay switch 6 is conductive,
Flip-flop 29 is reset.

On the other hand, by AND-tying the delayed outputs of the inverting circuits 53 and 54, the fifth
A trigger pulse shown in FIG. 8 is derived. This trigger pulse is applied to the monostable circuit 9 via the OR gate G12, and one pulse is derived from the monostable circuit 9. This pulse is applied to AND gates G1, G
2 and the latching relay 8 is now reset, the reset output of the flip-flop 29 is applied to the semiconductor switching circuit 7, and the latching relay 8 is reset.

The set output Q of flip-flop 29 is AND
It is connected to one input terminal of the gate G1 and also to the edge detector circuit 61. The edge detector circuit 61 is a flip-flop 29
A pulse is generated by detecting the edge of the rising or falling edge of the set output Q, and this pulse is applied to the monostable circuit 9 via the OR gate G12.

FIG. 6 is a circuit diagram showing the configuration of the monostable circuit 9. In the monostable circuit 9, the output of the OR gate G12 is given to the base of the transistor TR12. The output of the constant voltage circuit 10 is applied to the emitter of the transistor TR12 from a terminal 67 via a series circuit consisting of a resistor 65 and a diode 66. A series circuit consisting of a resistor 68, a transistor TR13, a resistor 69, and a transistor TR14, and a resistor 7 are connected in parallel with the series circuit consisting of a resistor 65, a diode 66, and a transistor TR12.
A series circuit consisting of 0, a diode 71, and a resistor 72, and a series circuit consisting of a transistor TR15, a resistor 73, and a resistor 74 are connected. Further, a series circuit consisting of transistors TR16, TR17, TR18 and a resistor 75 is provided in parallel with each of the series circuits, and transistors TR16, TR1
A series circuit consisting of transistors TR19 and TR20 is connected in parallel with transistors TR19 and TR20. Transistor TR1
The emitter of transistor TR14 is connected to the base of transistor TR14 through a diode 76.
The collector of TR13 is connected to capacitor 77. The bases of transistors TR13, TR16, and TR19 are commonly connected, and the transistors
The collector of TR14 is connected to the base of transistor TR17, and transistors TR16 and TR1
The connection point between diode 71 and resistor 72 is connected to the base of transistor TR15, and the connection point between diode 71 and resistor 72 is connected to the base of transistor TR20.
The connection point between resistors 73 and 74 is transistor TR21
This transistor TR21 is connected to the base of
An output pulse is derived on line 78 connected to the collector of. The base and collector of a transistor TR22 are connected to the base of the transistor TR18, and the base of the transistor TR22 is connected to the terminal 67 via a resistor 79.

In such a monostable circuit 9, the transistor TR12 is normally conductive, and current flows through the resistor 65 and diode 66. In order to reduce this power consumption, resistor 6
It is necessary to increase the value of 5, but this resistor 65
It is monolithic to increase the value of
It is not preferred in ICs etc. from the viewpoint of chip size and accuracy. However, since the diode 66 is connected in series with the resistor 65, the voltage applied to the resistor 65 is equivalently reduced, and current consumption is reduced accordingly.

Generally, the output pulse width of a monostable circuit is determined by external resistors and capacitors in monolithic ICs. Here, if it is necessary to reduce the number of external parts due to mounting reasons,
As shown in the figure, the resistance can be provided by an internal circuit. However, their resistance values are
Since it is on the order of IMΩ, in this embodiment, the capacitor 77 is charged from a constant current circuit consisting of a resistor 68 and a transistor TR13. In this way, the transistor
Since the current value of the constant current circuit flowing through TR19, TR20 and resistor 75 changes according to temperature changes, there is a drawback that the output pulse changes greatly depending on the temperature conditions. Therefore, transistor TR18,
Resistor 75, resistor 79 and transistor TR22
By providing a constant current circuit consisting of a transistor TR2 and a diode 71,
Keep the voltage between the base and emitter of 0 constant. Thereby, transistors TR19, TR20,
The current flowing through TR18 and TR21 remains constant regardless of temperature changes, and therefore the temperature characteristic of the output pulse width of monostable circuit 9 becomes flat.

In such a monostable circuit 9, an output pulse is derived on line 78 in response to a trigger pulse inputted via OR gate G12. The pulse width of this pulse is adjusted by changing the capacitance of the capacitor 77, and the latching relay 8
is chosen to be greater than the time required for it to operate.
The pulse derived on line 78 is the AND gate G
1, given to the other input terminal of G2, and
It is applied to AND gate G8 via inverting circuit 80. Therefore, the output pulse of the monostable circuit 9 is
It is used to select whether to operate the set side circuit or the reset side circuit of the semiconductor switching circuit 7. The semiconductor switching circuit 7 operates only when a pulse is derived from the monostable circuit 9, causing current to flow through the relay coil 13, and no current flows through the relay coil 13 once the latching relay 8 has finished operating. Therefore, power consumption is extremely low.

The output of AND gate G8 is flip-flop 2
9 clock terminal. Therefore,
When a pulse is derived from the monostable circuit 9, input signals from the toggle terminal T and the monostable terminal M are not accepted during that time. That is, the seventh
Even if a chattering input signal is applied to the AND gate G8 via the line 44 as shown in FIG. 1, during the pulse width T of the output pulse of the monostable circuit 9 shown in FIG. From then on, no signal is input to the clock terminal CK of the flip-flop 29, as shown in FIG. Therefore,
Chattering shorter than the pulse width T of the monostable circuit 9 will not cause malfunction. Regarding the reset signal and set signal,
The above considerations are not taken because even if there is chattering, once the flip-flop 29 operates, it will only maintain that state no matter how many times the reset and set operations are repeated. be.

FIG. 8 is a circuit diagram showing the configuration of the constant voltage circuit 10. A power supply voltage is supplied to the terminal 81 from a power supply (not shown). This terminal 81 has a transistor TR23, a resistor 82 and a transistor TR2.
A series circuit consisting of 4 transistors TR25,
Series circuit consisting of TR26, resistor 83, transistor TR27 and resistor 84, transistor TR
28, a series circuit consisting of TR29 and resistor 85, as well as resistor 86 and diode 87,8
A series circuit consisting of 8, 89, 90, 91, and 92 is connected in parallel. Transistor TR25, TR
The connection point 26 is connected to the base of the transistor TR23, and the transistor TR30 is connected between the terminal 81 and the base of the transistor TR23. The bases of transistors TR30, TR25, and TR28 are commonly connected. Transistor TR2
The connection point between 6 and resistor 83 is transistor TR2.
The base of the transistor TR29 is grounded via the transistor TR31, and is also connected via a diode 93 to the connection point between the diodes 89 and 90. transistor
A connection point between a resistor 83 and a transistor TR27 is connected to the base of TR31. A connection point 94 between the transistor TR23 and the resistor 82 is connected to the base of the transistor TR26, and a constant supply voltage is derived from a line 95 connected to the connection point 94 to terminals 26, 59, 63, and 67. .

Such a constant voltage circuit 10 keeps the voltage supplied to peripheral circuits such as the logic circuit 1 and the input interface circuits 2 to 5 constant even when the power supply voltage changes (4.75V to 15V). Here, since the diodes 87 to 89 were not provided in the conventional voltage regulator circuit, when the power is turned on, the regulator circuit 10 derives an output when the power supply voltage reaches three diodes, that is, 2.1V. Ta. Therefore, if the power supply voltage rises slowly, even if a pulse for autoset or autoreset is given to the semiconductor switching circuit 7, the supply voltage Vcc may be lower than the minimum operating voltage of the latching relay 8. , there was a risk that the latching relay 8 would not operate. However, constant voltage circuit 10
Since six diodes 87 to 92 are connected in series, the starting voltage of the constant voltage circuit 10 is 4.2V. On the other hand, the minimum operating voltage of the latching relay 8 is approximately 4.0V. Therefore, autoset or autoreset operation is reliably achieved for any rise in power supply voltage.

As another embodiment of the present invention, a noise removal circuit as shown in FIG. 9 may be used. In this noise removal circuit 95, the output of an inversion circuit 96 is applied to an inversion circuit 97 via a line 98. Further, the output of the inverting circuit 97 is given to a delay circuit 99,
The output of delay circuit 99 is wired and connected to line 98. The output of the inverting circuit 97 is line 1
00 and the delay circuit 10
1 and the output of the delay circuit 101 is applied to line 1.
Wired and connected to 00.

Referring to FIG. 10, if the waveform of the signal applied to the inversion circuit 96 is as shown in FIG. 10,
The output of the inverting circuit 96 is shown in FIG. 10, and the output of the delay circuit 99 is shown in FIG. 10, 3. Therefore, the signal given to the inverting circuit 97 is as shown in FIG.
The positive directional noise N ⁺ has been removed as shown in . The output of the inverting circuit 97 is shown in FIG. 10, and the output of the delay circuit 101 is shown in FIG. 10, 6. Therefore, the signal derived from the noise removal circuit 95 has N ⁺ and N ^- noises removed as shown in FIG. 10.

Such a noise removal circuit includes the first noise removal circuit 28 and the second noise removal circuit 3 shown in FIG.
5. Instead of the third noise removal circuit 39, it can be used for toggle signal lines and monostable signal lines. Moreover, the conventional noise removal circuit has six inverting circuits 102 to 102 as shown in FIG.
107 and two delay circuits 108, 109, two inverting circuits 96, 97 and 2 are required.
It is composed of delay circuits 99 and 101,
The circuit configuration becomes simpler.

As described above, according to the present invention, noise mixed in an input signal can be reliably removed using a noise removal circuit having a very simple configuration, and therefore malfunctions can be reliably prevented.

[Brief explanation of drawings]

Fig. 1 is an overall circuit diagram of an embodiment of the present invention, Fig. 2 is an overall circuit diagram of an embodiment of the present invention;
The figure is a circuit diagram of the input interface circuit 7.
4 is a circuit diagram of the second noise removal circuit 35, and FIG. 5 is a timing chart for explaining the operation in response to a signal from the auto-reset or auto-set terminal A. 6 is a circuit diagram of the monostable circuit 9, and FIG. 7 is a timing chart for explaining the signal input to the clock terminal CK of the flip-flop 29.
FIG. 8 is a circuit diagram of the constant voltage circuit 10, FIG. 9 is a circuit diagram of a noise removal circuit 95 according to another embodiment of the present invention,
FIG. 10 is a timing chart of the noise removal circuit 95, and FIG. 11 is a circuit diagram of a conventional noise removal circuit. 1...Logic circuit, 2-5...Input interface circuit, 6...Relay switch, 7...Semiconductor switching circuit, 8...Latching relay, 9
... Monostable circuit, 10 ... Constant voltage circuit, 11,1
4... Diode, 28... First noise removal circuit, 29... Flip-flop, 35... Second noise removal circuit, 36... Third noise removal circuit, 9
5... Noise removal circuit, TR1 to TR31... Transistor, R... Reset terminal, S... Set terminal, T... Toggle terminal, M... Monostable terminal, A... Auto-reset or auto-set terminal.

Claims (1)

[Claims] 1. Controls the switching mode of the relay switch of the latching relay by controlling the set output and reset output of the flip-flop in the logic circuit that responds to each signal from the input terminal and the auto-reset or auto-set terminal for controlling the operation of the latching relay. In a latching relay drive circuit that is applied to a semiconductor switching circuit for the purpose of is applied to a noise removal circuit that removes noise by deriving an output based on the coincidence with is,
A latching relay drive circuit characterized in that the signal line for setting and resetting the flip-flop is configured to remove only noise in a direction opposite to that of the signal for performing the set and reset operations.