JPH02105437A - Logic integrated circuit failure diagnosis method and device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method and apparatus for diagnosing faults in logic integrated circuits using a non-contact tester.

[Conventional technology]

One example of a fault diagnosis method for logic circuits is "Fault Diagnosis of Digital Systems" (
Fault Diagnosis of Digital
1970 John Wiley 8 Sons
There is a method using a fault dictionary, as described in , I nc, ).

A fault dictionary is a correspondence table between malfunction output patterns and faults that may cause them, and is generally created in advance by simulation. However, the time required to create a fault dictionary on a computer increases in proportion to the square or cube of the number of elements included in the circuit to be diagnosed, so in large-scale integrated circuits, this fault dictionary cannot be created in a practical amount of time. It's becoming impossibly large. Therefore, the difficulty in diagnosing failures in logic integrated circuits increases rapidly as the number of integrated elements increases.

One effective way to solve the above problems is to provide testability design to logic integrated circuits.

For example, the proceedings of the 14th Design Automation Conference
the14th Design Autom
ation Conference, 1977)
LSSD (L
evel 5intensive 5can Desig
If method n) is used, test data can be directly set in the internal flip-flops, so conditions that determine the operation of circuits other than the flip-flops can be set. Therefore, since circuit division becomes easier, fault diagnosis of logic integrated circuits subjected to the LSSD method becomes considerably easier than when the LSSD method is not applied.

However, implementing testability design involves an increase in circuitry. Therefore, an increase in the chip size of integrated circuits, that is, an increase in cost, is unavoidable.

Therefore, not all current logic integrated circuits are designed to facilitate testability.

Even without testability design, a promising method for solving the above problems is to use a non-contact tester. For example, by irradiating the surface of an integrated circuit chip to be diagnosed with an electron beam and analyzing the energy of secondary electrons released, the potential of the wiring material can be determined.

An example of a fault diagnosis method for integrated circuits using this method is described in IEE "Design and Test of Computers," Volume 2, No. 5 (IEE "D"
esign & Te5t of Computers
There is a method shown on pages 74 to 82 of Vol. 2, No. 5, October 1985).

According to this method, first, the operation of the integrated circuit to be diagnosed is fixed in a state where a certain test pattern is applied. Then, when the surface of the integrated circuit chip at that time is inspected w4 with an electron beam tester, a wiring image reflecting the surface potential, that is, the logical state ("0" or 111 I+) of the top layer wiring can be obtained. On the other hand, an expected wiring image in the correct operating state is obtained using logic simulation and mask data. Fault diagnosis becomes possible by comparing the above vA survey line images and expected wiring images.

[Problem to be solved by the invention]

As described above, the method of diagnosing the failure of an integrated circuit using an electron beam tester is a method of diagnosing the failure of an integrated circuit that does not involve the addition of circuits and does not particularly require the creation of a failure dictionary. However, the above method of diagnosing faults in integrated circuits using an electron beam tester has the drawback that only fixed faults such as short circuits, disconnections, and degeneracy can be detected.

The present invention has been made in order to solve the above-mentioned drawbacks of the prior art, and provides a method for diagnosing failures of integrated circuits using a non-contact tester, which is particularly capable of detecting transient failures such as delays and hazards. The purpose is to

[Means to solve the problem]

The above objective is achieved as follows.

1. As a fault diagnosis method for logic integrated circuits, a test pattern is input to the input terminal of the integrated circuit to be diagnosed, and the observed waveform of the output terminal is compared with the expected waveform from logic simulation. If the two do not match, this is Detected as a malfunction output terminal.

Upon detection of a malfunctioning output terminal, the flip-flop to which the signal of the malfunctioning output terminal is coupled is determined from the logic connection file, the output signal of the flip-flop is observed with a non-contact tester, and the observed waveform and logic are The expected waveform from the simulation is compared and verified, and a flip-flop with a mismatch between the two is detected as a malfunctioning flip-flop.

If a malfunctioning flip-flop is detected, the flip-flop that is the source of the input signal of the malfunctioning flip-flop is found from the logic connection file using the same operation as above, and the output signal waveform of the flip-flop is measured using a non-contact tester [J! The observed waveform and the expected waveform are compared, and if they match for all flip-flops, the malfunctioning flip-flop is determined to be the malfunction source flip-flop,
Furthermore, if there is a flip-flop in which the above two do not match, an operation is performed to make that flip-flop a new malfunctioning flip-flop.

Furthermore, the above operation is repeated for the malfunctioning flip-flop to find the malfunction source flip-flop.

If a malfunction source flip-flop is detected, perform the above operation to find the input signal of the gate circuit directly connected to that input signal, proceed with the operation further, and if any of the input signals malfunctions, check that input signal. A gate circuit directly connected to the signal is found, and the above operation is repeated for this gate circuit to detect the fault location.

2. If a malfunction source flip-flop is detected in item 1, the output signal waveform is applied to the integrated circuit to be diagnosed using a non-contact tester again by slowing down the application rate of the test pattern, and then this is applied to a logic simulator. If the result of comparison and verification agrees, it is determined that the cause of the malfunction of the malfunction source flip-flop is a delay fault.

3. Furthermore, regarding failures diagnosed as delay failures,
The input signal of the gate circuit directly connected to the input signal of the flip-flop diagnosed as the malfunction source flip-flop was determined using a logic connection file, and the signal waveform was observed using a non-contact tester.

Determine the signal delay time of each input signal in the malfunctioning clock cycle. Then, the input signal with the maximum delay time is selected from among the input signals.

Furthermore, the input signal of the gate circuit directly connected to that input signal is obtained, and the same processing is performed on this, and this processing is repeated until the gate circuit becomes a flip-flop.

Then, the route connecting the gate circuits determined in this manner is diagnosed as a delay failure route.

4. In the above fault diagnosis method, the logic simulator is a function simulator at the register level. Alternatively, the logical connection file may be described using logical relational expressions at the register level.

5. As a fault diagnosing device for a logic integrated circuit, part or all of the fault diagnosing procedure in the fault diagnosing method for a logic integrated circuit described in items 1 to 4 above is stored as a computer program in its memory.

As part of the fault diagnosis procedure, for example, if only the first term is included, the fault location can be diagnosed, if the second and third terms are included, delay failures can also be diagnosed, and if the fourth term is included, the fault location can be diagnosed. This has the advantage that failure diagnosis can be performed efficiently.

[Effect]

In the present invention described in item 1 of the means, since the electron beam or laser beam is focused on a specific point and irradiated, it is possible not only to easily obtain the potential waveform of the signal at that part, but also to easily obtain the potential waveform of the signal at that part. Therefore, there is no need to fix the operation of the integrated circuit. Therefore, the method of the invention comprises:
This makes it possible to detect not only fixed faults such as short circuits, disconnections, and degeneracy, but also transient faults such as circuit delays and hazards.

In addition, as a method for diagnosing the failure location, first, we search for the malfunction source flip-flop at the flip-flop level.
Once the malfunction source flip-flop has been determined, the cause of the malfunction, that is, the cause of the malfunction, exists between the malfunction source flip-flop and the flip-flop that is the source of its input signal. Adopt a hierarchical method of searching. At this time, whether or not the flip-flops and gates are operating correctly is determined by comparing the observed waveform with the expected waveform obtained through simulation. Therefore, the fault diagnosis method of the present invention enables efficient fault diagnosis of integrated circuits in a short time even without a fault dictionary.

A delay fault is a fault that occurs due to a large circuit delay. Therefore, if the malfunction disappears by slowing down the speed of the test pattern as described in item 2 of the means above, it can be seen that the malfunction was due to circuit delay. Since the method of the present invention does not require fixing the circuit operation, it is possible to detect such faults separately from fixed faults.

For delay failures, it is necessary to detect gates with an abnormally large delay time or routes where the cumulative delay time is abnormally large. The method described in item 3 of the means effectively detects the location and route of such a failure.

Using the logic simulator as a register-level simulator as described in item 4 of the means does not require precise simulation of all circuit elements, reducing the time required for simulation and making diagnosis more efficient. It is intended to be a target. Also, if you write the logical connection file using logical relational expressions at the register level,
For example, it is now possible to immediately know which flip-flop's input signal is connected to which flip-flop's output signal, making fault diagnosis processing faster and more efficient.

Item 5 of the above means indicates means for effectively applying the method of the present invention to an apparatus.

[Example] FIG. 1 is a diagram showing an example of the overall configuration of an apparatus used in the failure diagnosis method of the present invention.

In FIG. 1, 1 is an integrated circuit chip to be diagnosed, 2 is a flip-flop or memory element included in the integrated circuit 1 to be diagnosed, and 3 is also included in the integrated circuit 1 to be diagnosed, and This is a combinational circuit section that generates input signals for flip-flops.

Next, the electron beam tester 4 irradiates an electron beam onto llilll points and detects the energy of secondary electrons generated there, thereby observing the signal potential at that observation point.

Next, the observation signal processing device 5 is a device that creates waveform data based on the potential of the wi measurement point obtained by the electron beam tester, and if necessary, it converts this data into logical information waveforms of O and 1 according to instructions from the computer 8. It has the function of converting to .

Next, the position control device 6 is a device that determines the observation point for the electron beam tester 4. In order to determine the position to be irradiated with the electron beam, the position control device 6 determines the amount of movement of the sample stage and the deflection angle of the beam, and uses the electron Send to beam tester 4.

Next, the LSI tester 7 supplies a test pattern to its input terminal in order to operate the integrated circuit chip 1 to be diagnosed.
It is also a device for detecting the output signal of the output terminal.

The test pattern used here is generated by the computer 8 and sent to the LSI tester 7 using a magnetic tape or a communication line.

Next, in the memory inside the large computer 8.

Information and processing procedures for diagnosing the integrated circuit chip 1 to be diagnosed as shown in FIG. 2 are stored.

Note that the memory here refers to a main memory or a secondary memory such as a disk, and the same applies hereinafter.

In FIG. 2, numeral 11 is a layout file for creating a mask for the integrated circuit chip 1 to be diagnosed, which stores graphic information and position information of elements and wiring mounted on the chip.

Next, 12 is a file that stores connection information of the logic circuit elements of the integrated circuit chip 1 to be diagnosed, and 13 is a file that stores a test pattern to be applied from the input terminal of the integrated circuit chip 1 to be diagnosed to operate it. It is a file.

Next, 14 is logical connection information 1 of the integrated circuit chip 1 to be diagnosed.
This is expected waveform data of an output terminal or an internal signal obtained as a result of simulating the operation of the integrated circuit chip 1 to be diagnosed using the logic simulator 17 using the test pattern 13 and the test pattern 13 as input data. In addition, 15 is an electron beam tester 4
This is observed waveform data that was observed by the observed signal processing device 5 and converted into information by the observed signal processing device 5.

Observed waveform data 15 of signals on the integrated circuit chip 1 to be diagnosed
is subjected to comparison processing 16 with expected waveform data 14,
This will determine whether the observed waveform data is correct, that is,
It is determined whether the a-open signal on the integrated circuit chip 1 to be diagnosed is operating correctly.

Next, the results of the comparison and verification process 16 are reported to the fault location diagnosis process 18. If the location of the failure cannot be determined in this process, the source signal of the signal determined to be malfunctioning in the comparison and verification process 16 is determined using the logical connection file 12.

Next, the wiring position coordinates on the integrated circuit chip 1 to be diagnosed of the signal determined in the fault location diagnosis processing 18 are determined using the logical connections 12 and the layout file 11, and the coordinates are calculated by the position control device 6.
send to

FIG. 3 is a diagram showing a procedure for performing fault diagnosis according to the present invention.

When performing this procedure, it is assumed that the test pattern 13 and expected waveform data 14 for the integrated circuit chip 1 to be diagnosed have already been created, and these are transferred to the LSI tester 7, and the integrated circuit chip 1 to be diagnosed is It shall be in working condition or ready to operate immediately.

In FIG. 3, the steps p1 to p3 are generally performed using the LSI tester 7. The LSI tester 7 applies a test pattern to the integrated circuit chip 1 to be diagnosed, operates it, and takes out the response signal from the output terminal (procedure pi). Next, in the LSI tester, the waveform of the response signal obtained from the output terminal is compared with the expected waveform data 14 (hand J@p2
). As a result, it is determined whether the output signal of the terminal is correct (step p3).

By repeating the above steps, malfunctioning output signals are detected.

Next, the source of the detected terminal output signal malfunction is investigated. To do this, first, using the logical connection file 12, it is determined to which internal flip-flop the terminal output signal is coupled via various gate circuits (step p4).

For example, if there is a circuit as shown in FIG. 4, in step p4 here, FFI, FF2 . FF3. Find FF4.

In Fig. 4, PADI is the output terminal where malfunction was discovered, IVI and IV2 are the inverter circuits, and NAI to NA3.
is a NAND circuit, NRI is a NOR circuit, FFI to FF4
is a flip-flop.

Figure 5 (a) shows an example of describing the logical connections for the circuit in Figure 4.
Shown below. Moreover, the description format at this time is shown in FIG. 5 (b). That is, the 1111th part of the connection description is the element name, that is, the name of the gate or flip-flop. This is also used as the output signal name of that element. Next, the function of the element is described in the second column, and the input signal name string is described in the third column. Here, what can be used as the input signal name is the element name, that is, the name that appears in the 1mth position. Also, if there are multiple input signals, separate them with a comma (1) and write them. Furthermore, each of the first to third columns is separated by one or more blank spaces.

FIG. 6 shows a flowchart of a method for searching for a flip-flop that is the source of a malfunction signal when there is connection information as described above.

First, the name of the malfunction signal is set as the search signal name (p21).

Next, the same name as this search signal name is searched from each element column of the connection description (p22, p23).

Next, the input signal written in the row of the matched element name is temporarily entered into the search special signal table (p24). It is okay for two or more signal names to be entered at the same time, but check whether the same signal name has already been written or has been written, and if so, do not write it.

Next, one signal name is extracted from the search signal table. At this time, if the table is already empty, the process ends. Also, if it is not empty, the signal name is used as the search signal name (p25, p26).

Next, the same name as this search signal name is searched in each element column of the connection description (P27, P28).

Next, check whether the description of the matching row is a flip-flop (p. 29). As a result, if it is a flip-flop, its name (element name) is entered in the flip-flop table, and the process returns to p25 to continue the process. If not, return to p24 and continue the process.

When the above processing is completed, the flip-flops written in the flip-flop table are as follows.

This is the source of the malfunction signal.

When the source flip-flop of the malfunction signal is detected, these signal waveforms are observed with an electron beam tester (p5).
Next, it is compared and verified with the expected waveform data 14 obtained by the fIA waveform waveform physics simulator 17 (p6).This comparison and verification is performed at a specific discrete timing in which both the observed waveform 1 and the expected waveform are synchronized with the basic clock. This is performed on the data converted to level 1.

If there is no match in this comparison, it means that the flip-flop is malfunctioning, and the process returns to step p4 to search for the source of this malfunction. Also.

If all the flip-flops entered in the flip-flop table match, the source of the malfunction is a combination surrounded by those flip-flops and the flip-flop or output terminal that was the first signal in the search process in Figure 5. It will be in the part.

Therefore, the flip-flop or output terminal that is the first signal in the search process is referred to as the malfunction source flip-flop (p9).

Taking Fig. 4 as an example, if there is a malfunction at the output terminal PAD1, but there is no malfunction at the flip-flops FFI to FF4, the output terminal PAD1 is the malfunction source flip-flop, and the source of the malfunction, that is, the failure location, is from the output of FFI to FF4. P.A.
It exists between Dl.

If the malfunction source flip-flop is found, its input signal is observed (plo). This IT measurement waveform is then compared and verified with the expected waveform obtained by logic simulation (
p 11), this comparison and verification is not a level comparison of 0 and 1 at discrete timing, but a comparison as shown in FIG. 7.

FIG. 7(a) is a logical symbol diagram of a D type flip-flop. Here, D is a data input, φ is a clock input, and Q is a flip-flop output signal.

Comparison and verification are performed separately for clock input and data input.

FIG. 7(b) shows an example where a mismatch occurs in the comparison and verification of clock input signals. First, although a clock (signal that changes from O → 1 → 0) exists in the clock expected waveform, it does not exist in the vA measurement waveform (a), or even if it exists, its clock width or level If (b) is abnormally small, it is determined that there is no match. Furthermore, cases (c) where noise or glitches are present in the [111 waveform] and cases (d) where a clock is present even though there is no clock in the expected Tarock input waveform are also considered to be inconsistent.

FIG. 7(c) shows an example where data input signals are compared and verified to be inconsistent. First, the timing of the change from 0 to 1 or 1 to 0 in the iR measured waveform of the data input is significantly delayed compared to the expected waveform, and moreover, the timing of the change from 0 to 1 or 1 to 0 in the iR measured waveform of the data input is significantly delayed, and moreover, the clock cycle is II! This is the case (e) when a correct clock exists in the clock input waveform and the delay of the expected waveform is after the falling edge of the observed clock input waveform, and the expected waveform is This is a case where the observed waveforms are different from each other (f).

If the observed waveform of the input signal of the flip-flop matches the expected waveform in the above comparison, then the fault lies in the flip-flop itself.

Also, if there is a signal that does not match in the above comparison, the signal (gate output signal) one gate before generating that signal is searched for using the logic connection file 12 (
p 13).

Next, the waveform of the gate output signal searched above is observed with an electron beam tester, and compared with the expected waveform (p14, p15). The method of comparison and verification here is based on the method shown in FIG. 7(b) for comparison and verification on the clock input signal side. Comparison and verification on the data input side is performed only based on whether the signals match over the relevant clock cycle or whether the changes in the signals match.

Next, if a discrepancy occurs in the above comparison,
Return to page 13 and further explore the source of the malfunction (p 16)
. Furthermore, if no mismatch occurs, the failure is due to a failure in the gate to which the compared and verified signals are input (p17).

Faults that can be diagnosed in the manner described above are so-called fixed faults such as disconnection, short circuit, and degeneracy. Also,
Hazards and glitches can be detected for clock inputs.

FIG. 8 shows an example of how hazards and glitches can be detected. Figure 8 (a) is an example of the circuit, FFl0
is a D-type flip-flop, where D is the data input, φ is the clock input, and Q is the output. Further, IVIO is an inverter circuit, and NA10 is a NANDA path.

FIG. 8(b) is an example of a timing chart of the operation. It is assumed that signal A changes from 1 to O, and signal B changes from O to 1 in a certain clock cycle.

However, if the circuit delay of signal A is larger than the circuit delay of signal B, it is possible that the clock φ is active (level 1).
Assume that it depends on the area. Then, a glitch occurs in the output of NA10. This is also transmitted to the output of IVIO, causing FF10 to malfunction.

Diagnosing this using the method described above, first, FF10 is found as the malfunction source flip-flop. When its input is examined next, there is a glitch in the clock input, ie, IVIO, which does not match the expected waveform. Furthermore, there is a glitch in the output of the gate NA10 just before that, and this also does not match the expected waveform. However, NAl
When the input is 0, all of the signals A, B, and φ match the expected waveforms. As a result, NA10 is determined to be faulty.

Next, a method for detecting a delay fault using the fault diagnosis method described above will be described.

A delay failure is a failure that occurs due to a large circuit delay, and FIGS. 7(c) and 7(e) correspond to it.

Furthermore, a glitch as shown in FIG. 8(b) can also be called a delay failure.

To distinguish between fixed faults and delayed faults like the one above,
When the malfunction source flip-flop is detected (that is, after p9 in FIG. 3), the operating speed of the integrated circuit chip 1 to be diagnosed is slowed down.

That is, the frequency of the basic clock input to the chip is slowed down. In this way, if the operation of the malfunction source flip-flop becomes correct, that is, if the fit measurement waveform and the wait waveform match, the cause of the malfunction is determined to be a delay failure.

FIG. 9 shows an example of a waveform of a delay failure. Figure 9 (a) is a logic symbol diagram of a D type flip-flop, where Q is the output of the flip-flop, D is the data input,
φ indicates a clock input.

Moreover, FIG. 9(b) is an example of a waveform when a delay fault exists, and the delay time of the D input is so large that it is not taken into the flip-flop by the clock of that cycle. FIG. 9(C) is a waveform example for the same operation as in FIG. 9(B) when the clock frequency is slowed down. In this case, although the clock cycle time becomes longer, the delay time of the D input is constant, so changes in the D input are taken into the flip-flop in the same cycle as changes caused by the clock φ.

In the case of a delay failure, the failure includes a failure in which the delay time of a specific gate is abnormally large, and a failure in which the integrated value of the delay time of each gate becomes too large. In the latter case, the failure location is not at a specific gate but on a specific route.

For delay failures, it is essential to know which gates and routes have abnormally large delay times as described above.

FIG. 1O shows the procedure for detecting gates or paths of delay faults. The procedure will be explained with reference to FIG. Note that FIG. 11(a) is an example of a circuit for explanation, and FFII to FF15 are flip-flops,
NA15. NAl6 is a NAND circuit, NR15, NR1
6 is a NOR circuit.

In FIG. 11(a), it is assumed that the FF 15 is a malfunction source flip-flop, and the malfunction is determined to be a delay failure on the data input side. At this time, first, the input signal of this FF15 (the part indicated by (01)) is observed with an electron beam tester, and the waveform shown in FIG. 11 (b) (01) is obtained (p
lot).

Next, the gate NA15 outputting the signal (01) and its input signals (02) and (03) are searched for using the logical connection file 12 (p 102).

Next, the waveforms of the input signals (02) and (03) are observed using an electron beam tester (p. 103). Examples of the waveforms are shown in FIG. 11 (b) (02) and (03).

Next, the delay times of these two input signals are compared and the larger one is selected (P104). In this example, the input signal (03) has a larger delay time.

Next, proceeding to step p105, it is determined whether the signal (03) is a flip-flop output. Here, since it is not yet a flip-flop, we return to hand 11plO2 and input the input signal of gate NR15 which is generating (03) (
04) and (05).

Next, the waveforms of the signals (04) and (05) are observed using an electron beam tester, and their delay times are measured (FIG. 11(b)). Here, the signal on the (04) side is fixed at 1'0'' in this clock cycle, so it has nothing to do with the delay failure. Therefore, in this case, the signal on the (04) side
Select 5).

Next, the input signals (06) (07) of the gate NR16 connected to the signal (05) are selected, these are observed with an electron beam tester, and the maximum delay signal (06) is selected.

As a result of the above, in the circuit of Fig. 11 (a), FF14→NR
It can be seen that the path 16→NR15→NA15→FF15 has the maximum delay6. In other words, this route can be said to be the location of the delay failure.

Further, a delay fault in which a specific gate delay time is abnormally large can be detected by finding the delay time difference in the process of finding the path of the delay fault.

Next, it will be shown that the fault diagnosis method described above can be performed more efficiently if there is a function simulator at the register level and a logical relationship between registers (pool-like expression).

In the procedure from P1 to P9 in FIG. 3, only the malfunction of the flip-flop is a problem, and the connection relationship at the gate level is completely ignored. Therefore, here, to create the expected output value of the flip-flop, a functional simulator at the register level is used instead of a logic simulator at the gate level. That way, the time required for simulation is shorter.

Further, if the connection relationship between registers is described using a pool type, the processing shown in FIG. 6 becomes unnecessary. For example, the D input of FF15 and FFII to FF1 in Figure 11 (a)
If the relationship of 4 is written as a pool formula, FF15(D)=F
F11・FFT? (・F7T? 10FF12-1'7T'
It becomes J-F1'TT. If you look at this formula, FF15's D
Since it is immediately known which FF's output signal the input signal is connected to, the processing shown in FIG. 6 is not particularly necessary. The fault diagnosis process becomes faster accordingly.

〔Effect of the invention〕

As explained above, the present invention is a method of measuring the operating waveform wA using an electron beam tester while operating an integrated circuit, and comparing it with the expected waveform obtained by simulation. Without the need for a test circuit, it is possible to diagnose not only fixed faults such as short circuits, disconnections, and degeneracy, but also transient faults such as delays and hazards.

Furthermore, since the diagnosis is performed separately at the flip-flop level and the gate level, the efficiency of narrowing down the failure is improved compared to diagnosing only at the gate level. Moreover, the efficiency of diagnosis is further improved by register-level logic description and a functional simulator.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of the overall configuration of a device used in the failure diagnosis method of the present invention, Fig. 2 is a diagram showing the diagnosis processing procedure stored in the memory of the computer and the configuration of the information files necessary therefor, and Fig. 3 is Figure 4 is a diagram showing a specific processing procedure for fault diagnosis. Figure 4 is a specific example of a partial circuit of the circuit to be diagnosed. Figure 5 is a specific example of a logical connection description for the circuit in Figure 4. Figure 6 is a diagram showing a malfunction source flip-flop. A diagram showing the diagnostic processing procedure for detecting
Figure 7 is a diagram showing an example of a mismatch in waveform comparison, Figure 8 is a diagram explaining that glitches can be detected, Figure 9 is a waveform example of a delay fault, and Figure 10 is a diagram diagnosing a delay fault. FIG. 11 is a diagram illustrating the procedure for diagnosing a delayed fault, and shows an example of a circuit and an example of its waveform to explain the delay fault diagnosis. 1... Integrated circuit chip to be diagnosed 2... Flip-flop 3... Combinational circuit 4... Electron beam tester 5... Observation signal processing device 6... Position control device 7... LSI tester 8 ... Computer 11 ... Layout file 12 ... Logical connection file 13 ... Test pattern file 14 ... Expected waveform data file 15 ... Observed waveform data file 16 ... Comparison and verification processing program 17.・Logic simulator 18... Fault location diagnosis program 19...Next It measurement signal coordinate calculation program Attorney Junnosuke Nakamura Diagram PADloUT IVi IVi INV NA1 AI A2 NRI V2 A3 NAND NA2. NRI NAND FFI, I2 NORFF2. IV2 INV NA3 NAND FF3 FF4 (a) Keiko name Riko (b) Input 77 signal name Figure (a) (b) Figure 7 Figure 6 Figure 8 (a) (b) Figure 9 Figure 10

Claims (1)

[Claims] 1. A failure of a logic integrated circuit in which a test pattern is input to the input terminal of the logic integrated circuit, and the signal waveform at the output terminal of the logic integrated circuit or a required location within the logic integrated circuit is observed to determine the location of the failure. In the diagnosis method, the observed waveform of the above output terminal is compared with the expected waveform obtained by logic simulation, and if the two do not match, it is detected as a malfunctioning output terminal. Find the flip-flop to which the signal of the malfunction output terminal is coupled from the logic connection file, observe the output signal of the flip-flop with a non-contact tester, and compare and match the observed waveform with the expected waveform from the logic simulation. detecting mismatched flip-flops as malfunctioning flip-flops; if a malfunctioning flip-flop is detected;
Find the flip-flop that is the source of the input signal of the malfunctioning flip-flop from the logic connection file using the same operation as above, observe the output signal waveform of the flip-flop with a non-contact tester, and compare and match the observed waveform with the expected waveform. , when the two match for all flip-flops, the malfunctioning flip-flop is set as the malfunction source flip-flop, and if there is a flip-flop for which the two do not match, the flip-flop is set as a new malfunctioning flip-flop; Furthermore, repeat the above operation for the malfunctioning flip-flop to find the malfunction source flip-flop, and if the malfunction source flip-flop is detected, use the above procedure to find the input signal of the gate circuit directly connected to that input signal. Further operations are performed on the input signal, and if there is a malfunction with respect to the input signal, a gate circuit directly connected to the input signal is found in the same manner, and the above operation is repeated for this to detect the failure location. Fault diagnosis method for logic integrated circuits. 2. If a malfunction source flip-flop is detected, its output signal waveform is observed again using a non-contact tester by slowing down the application rate of the test pattern applied to the integrated circuit under diagnosis, and this is compared to the expected value determined using a logic simulator. The logic integrated circuit according to claim 1, characterized in that the waveform is compared and verified, and if the results of the comparison and verification match, the cause of the malfunction of the malfunction source flip-flop is diagnosed as being a delay fault. Fault diagnosis method. 3. For failures diagnosed as delay failures, the input signal of the gate circuit directly connected to the input signal of the flip-flop diagnosed as the malfunction source flip-flop is determined using a logic connection file, and the signal waveform is measured in a non-contact manner. Observe with a tester, determine the signal delay time of each input signal in the malfunctioning clock cycle, select the input signal with the maximum delay time among the input signals, and select the gate directly connected to the input signal. Find the input signal of the circuit, perform similar processing on it, repeat this processing until the gate circuit becomes a flip-flop, and define the path connecting the gate circuits found in this way as the delay failure path. 3. A method for diagnosing a fault in a logic integrated circuit according to claim 2, further comprising diagnosing a fault in a logic integrated circuit. 4. The logic according to claims 1 to 3, wherein the logic simulator is a function simulator at a register level, or the logic connection file is a logic relational expression at a register level. Fault diagnosis method for integrated circuits. 5. means for applying a test pattern to the integrated circuit to be diagnosed; a non-contact tester for observing waveforms at required observation points in the integrated circuit to be diagnosed; and observation signal processing means for creating observed waveform data from the output thereof; Diagnosing the failure of an integrated circuit to be diagnosed by having a position control means for determining the observation position by a non-contact tester, and a computer that performs arithmetic processing, control, etc. for these means or based on information from these means. In the logic integrated circuit fault diagnosis device, part or all of the fault diagnosis procedure in the logic integrated circuit fault diagnosis method according to claims 1 to 4 is stored in its memory as the computer program. A failure diagnosis device for logic integrated circuits, which is characterized by: