JPH0210572A - Control device for reproducing device - Google Patents

Abstract

PURPOSE:To stably generate a speed error and to attain a highly accurate control by making a counter active only in a clock where a parity OK can be obtained. CONSTITUTION:A counter 9 counts only in a PLL block obtained in the block where the parity OK has been obtained, and a counter 10 counts a reference clock 11 only when the counter 9 counts. The counted values obtained by the counters 9 and 10 are inputted to a speed error detecting circuit 12, and the speed error is generated. When a parity checking circuit 5 outputs a parity NG as a parity detecting signal 5a, an output 8a of a holding circuit 8 becomes low, the counters 9 and 10 are not made active, counting is not executed, and the counters are made into a wait condition. Consequently, the parity detecting output 5a cannot be obtained, a PLL clock 3 is not counted in a period TNC when the PLL clock is not correctly obtained, and an erroneous speed error 13 is not outputted at error touch timing Tel.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control device for a reproducing device that obtains an output for driving a controlled object using a PLL clock obtained from a reproducing signal.

[Conventional technology]

First, the conventional technology will be explained. FIG. 4 is a block diagram showing an example of the prior art. 1 is a playback signal RF read from the recording medium, 2 is a PLL that generates a clock synchronized with the playback signal RF1, 2a is playback data obtained from the playback signal, 3 is a PLL clock synchronized with the playback signal RFI, and 4 is a PLL clock that is synchronized with the playback signal RFI. day modulator for converting playback data 2, 4a
5a is the converted playback data; 5 is a parity check circuit for detecting parity OK from the converted playback data;
is a parity detection result, 6 is a counter that detects a symbol that is the minimum configuration of reproduced data from PLL clock 3, and 7
a is a signal that activates the day modulator 4, 7b is a signal that activates the parity check circuit 5, 14 is a counter that counts the number of times the parity detection result 5a is OK, and 15 is a frequency divider that divides the PLL clock 3. 15a is a frequency-divided clock of the PLL clock 3, 16 is a counter that counts the period of the frequency-divided clock 15a using the reference clock 17, and 18 is a frequency-divided clock 15 for the output result of the counter 16.
The first latch latches at timing a, 19 is the first
A second latch 13 performs latching when the counter 14 counts a predetermined number of latched results by the latch 18. Reference numeral 13 is a speed error signal output from the second latch 19.

Furthermore, FIG. 2 shows the data structure of the DAT. In the figure,
5sync 8bit is a synchronization signal 8bit, Main I
D Wl, W2. Parity 8 bits are the first and second words of the main identification code, 8 pits each of parity, and Main Data 256 bits.
ts is main data of 256 bits.

Next, the operation will be explained using the operation waveforms shown in FIG.

The reproduced signal RF1 read from the recording medium is PL'L2
is input. PLL2 outputs reproduced data 2a and PLL clock 3. The PLL clock 3 is input to the counter 6, where a symbol, which is the smallest unit of reproduced data, is detected and a signal is generated to activate the day modulator 4 and the parity check circuit 5. Output a and 7b. In the day modulator 4, the playback data 2a is input, and upon receiving the day modulator activation signal 7a, the playback data 2a is converted and outputted (4a).The parity check circuit 5 to which the converted playback data 4a is input is Upon receiving the parity check circuit activation signal 7b, the parity state is determined and a parity detection result 5a is output. When the parity detection result 5a is OK, when the counter 14 counts the number of OK outputs a predetermined number, for example, 5 times, the counter 14 indicates that the PLL is locked.
A lock signal 14a is output. However, this count of five times is the number of counts within the period in which the reproduced signal RFI exists. On the other hand, the PLL clock 3 is frequency-divided by a frequency divider 15 to become a frequency-divided clock 15a. counter 1
6, the period of the frequency-divided clock 15a is measured by the reference clock 17. The measurement result is latched in latch 18. The result latched by the latch 18 is newly latched at the timing when the PLL lock signal 14a is obtained, and the latched result is considered as a speed error of the reading device that reads information from the recording medium and is output (13).

[Problem to be solved by the invention]

The conventional control device is configured as described above, and determines PLL lock based on the number of parity OKs at the end of period measurement of the divided clock, and does not check the lock state during period measurement. Therefore, the number of outputs of the parity detection output 5a is not 5 as shown in FIG.
When the L lock cannot be obtained, the period measurement of the divided clock 15a causes an error (error) at the latch timing Tej! However, there is a problem in that an incorrect speed error signal 13 may be output.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a control device for a playback device that can stably generate speed errors.

[Means to solve the problem]

A control device for a playback device according to the present invention is an oscillation unit that generates a clock synchronized with a playback signal obtained from the playback device in a control device that controls the playback device using playback data including reading accuracy judgment data obtained from a recording medium. a detection means for detecting reading accuracy information from reading accuracy judgment data included in the reproduced signal; a holding means for holding the result of the detection means for a certain period of time; a first counting means for counting output signals; a second counting means for counting a predetermined reference oscillation while the first counting means is counting; and error detection means for outputting an error signal for driving the controlled object from the value obtained by the second counting means.

[Effect]

In this invention, the detection result of the obtained reading accuracy information, that is, the parity state, is held for one block length, so that the speed error can be generated only by the correctly obtained PLL clock.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 7c is a signal 8 that activates the hold circuit 8 generated from the symbol detected by the counter 6.
8 is a hold circuit that holds the parity detection result 5a until the parity detection result 5a generated from the next block is obtained, 8a is a signal obtained by holding the parity detection result 5a for one block length, and 9 is a signal indicating that the parity detection result 8a is OK.
During this time, a counter that counts PLL clock 3, 10
is the reference clock 11 while the parity detection result 8a is OK.
12 is a speed error detection circuit that detects a speed error from the count values of counters 9 and 10.

Next, the operation will be explained using the operation waveform diagram in FIG. Parity detection result 5a indicates parity OK, hold circuit 8 is activated by hold circuit activation signal 7C, holds the parity OK state for one block length, and outputs parity detection result 8a indicating parity OK for one block length. . The counters 9 and 10 count only when the parity detection result 8a is in the parity OK state.

That is, the counter 9 counts only with the PLL clock 3 obtained in the block where parity OK is obtained (only during the period when the parity OK hold output in FIG. 3(b) is high), and the counter 10 counts The count value obtained from the counter 9.10, which counts the reference clock 11 only during the time when the reference clock 11 is running, is input to the speed error detection circuit 12, and a speed error is generated and output.

If the parity check circuit 5 outputs parity NG as the parity detection signal 5a, the output 8a of the hold circuit 8 in FIG. 3(b) becomes low (parity NG signal). The counters 9 and 10 are not activated, do not count, and are in a wait state. Therefore, the parity detection output 5a cannot be obtained,
The PLL clock 3 is not counted during the period TWC during which the PLL clock is not correctly obtained, so that the erroneous speed error 13 is not output even at the error latch timing Tel.

In this way, in this embodiment, the counters 9 and 10 are activated only in blocks for which parity is OK, and the PLL clock 3 and the reference clock 11 are counted, thereby generating a speed error and controlling the drive of the controlled object. Since the output is set to 13, a speed error can be stably generated and highly accurate control can be performed.

〔Effect of the invention〕

As described above, according to the present invention, the counter is activated only during blocks where parity is OK, so the accuracy of the obtained PLL clock increases, and the speed error obtained thereby increases the accuracy. It has the effect of becoming expensive.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a control device for a playback device according to an embodiment of the present invention, FIG. 2 is a diagram showing playback data, FIG. 3 is a diagram showing operating waveforms of the above embodiment, and FIG. 4 is a diagram showing a conventional control device. FIG. 5 is a diagram showing the control device of the playback device, and FIG. 5 is a diagram showing the operating waveforms of the conventional device. 1 is the reproduction signal RF, 2 is the PLL, 3 is the PLL clock,
5 is a parity check circuit (reading accuracy information detection means), 8 is a hold circuit, and 9.10 is a counter (first...
12 is a speed error detection circuit, and 13 is a speed error output.

Claims (1)

[Claims] (1) A control device that controls a playback device using playback data including reading accuracy judgment data obtained from a recording medium, comprising: oscillation means for generating a clock synchronized with a playback signal obtained from the playback device; a detection means for detecting reading accuracy information from reading accuracy judgment data included in the reading accuracy judgment data; a holding means for holding the result of the detection means for a certain period of time; and a signal output from the oscillation means according to the result of the holding means. a first counting means; and a second counting means for counting a predetermined reference oscillation while the first counting means is counting.
1. A control device for a playback device, comprising: counting means; and error detection means for outputting an error signal for driving a controlled object from the values obtained by the first and second counting means.