JPH02106833U - - Google Patents
Info
- Publication number
- JPH02106833U JPH02106833U JP1812490U JP1812490U JPH02106833U JP H02106833 U JPH02106833 U JP H02106833U JP 1812490 U JP1812490 U JP 1812490U JP 1812490 U JP1812490 U JP 1812490U JP H02106833 U JPH02106833 U JP H02106833U
- Authority
- JP
- Japan
- Prior art keywords
- support plates
- external
- lead
- monolithic
- main surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 2
- 238000007789 sealing Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 3
- 230000017525 heat dissipation Effects 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 1
Description
第１図は本考案の実施例に係わる絶縁物封止型
ハイブリツドＩＣを示す平面図、第２図は第１図
の―線に相当する部分の断面図、第３図は第
１図の支持板と外部リードとを示す平面図である
。
１，２，３，４，５，６……パワートランジス
タチツプ、７……ＩＣチツプ、８……回路基板、
９，１０，１１……支持板、１２，１３，１４…
…外部リード、１５……非連結外部リード、１６
……内部リード、１７……半田、１８……絶縁物
封止体、２１……配線導体、２３……貫通孔。
FIG. 1 is a plan view showing an insulator-sealed hybrid IC according to an embodiment of the present invention, FIG. 2 is a sectional view of a portion corresponding to the line - in FIG. 1, and FIG. 3 is a support shown in FIG. 1. FIG. 3 is a plan view showing a plate and an external lead. 1, 2, 3, 4, 5, 6... power transistor chip, 7... IC chip, 8... circuit board,
9, 10, 11...Support plate, 12, 13, 14...
...External lead, 15...Unconnected external lead, 16
...Internal lead, 17...Solder, 18...Insulator sealing body, 21...Wiring conductor, 23...Through hole.
Claims (1)
導出されていると共に放熱作用を有している複数
の支持板９〜１１と、 前記複数の支持板９〜１１の夫々の前記外部リ
ード１４が導出されている側の辺に対向するよう
に一端が配置され且つ前記外部リード１４に並置
され且つ前記複数の支持板９〜１１に対して連結
されていない複数の非連結外部リード１５と、 前記複数の支持板９〜１１の夫々に少なくとも
１個固着されている複数の半導体チツプ１〜６と
、 一方の主面上にモノリシツクＩＣ７が搭載され
ていると共にこのモノリシツクＩＣ７に対して電
気的に接続されている複数の配線導体２１を有し
、且つ前記複数の支持板９〜１１にまたがるよう
に配置されていると共に前記複数の支持板９〜１
１と前記複数の各非連結外部リード１５とにまた
がるように配置され、且つ前記一方の主面とは反
対の他方の主面が前記複数の支持板９〜１１側と
なるように配置されている回路基板８と、 前記複数の半導体チツプ１〜６の夫々と前記回
路基板８の前記複数の配線導体２１から選択され
たものとを接続する内部リード１６と、 前記回路基板８の前記複数の配線導体２１から
選択されたものを前記非連結外部リード１５に接
続する接続導体と、 前記複数の支持板９〜１１、前記外部リード１
４の一部、前記複数の非連結外部リード１５の一
部、前記複数の半導体チツプ１〜６、前記モノリ
シツクＩＣ及び前記回路基板８を被覆する絶縁物
封止体１８と から成る絶縁物封止型回路装置。[Claims for Utility Model Registration] A plurality of support plates 9 to 11 that are arranged in parallel with each other and from which external leads 14 are led out and have a heat dissipation function; and each of the plurality of support plates 9 to 11. A plurality of unconnected external parts, each of which has one end facing the side from which the external lead 14 is led out, is juxtaposed to the external lead 14, and is not connected to the plurality of support plates 9 to 11. A lead 15, a plurality of semiconductor chips 1 to 6 having at least one fixedly attached to each of the plurality of support plates 9 to 11, and a monolithic IC 7 mounted on one main surface, and a monolithic IC 7 mounted thereon. It has a plurality of wiring conductors 21 that are electrically connected to each other, and is arranged to span the plurality of support plates 9 to 11, and is arranged to span the plurality of support plates 9 to 1.
1 and each of the plurality of unconnected external leads 15, and is arranged so that the other main surface opposite to the one main surface is on the side of the plurality of support plates 9 to 11. an internal lead 16 connecting each of the plurality of semiconductor chips 1 to 6 with a selected one of the plurality of wiring conductors 21 of the circuit board 8; a connecting conductor that connects a selected wiring conductor 21 to the uncoupled external lead 15; the plurality of support plates 9 to 11; and the external lead 1;
4, a portion of the plurality of unconnected external leads 15, the plurality of semiconductor chips 1 to 6, the monolithic IC, and the insulator sealing body 18 that covers the circuit board 8. Type circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1812490U JPH0442942Y2 (en) | 1990-02-23 | 1990-02-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1812490U JPH0442942Y2 (en) | 1990-02-23 | 1990-02-23 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02106833U true JPH02106833U (en) | 1990-08-24 |
| JPH0442942Y2 JPH0442942Y2 (en) | 1992-10-12 |
Family
ID=31232486
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1812490U Expired JPH0442942Y2 (en) | 1990-02-23 | 1990-02-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0442942Y2 (en) |
-
1990
- 1990-02-23 JP JP1812490U patent/JPH0442942Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0442942Y2 (en) | 1992-10-12 |
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