JPH02106922A - Selective epitaxial growth method - Google Patents

Selective epitaxial growth method

Info

Publication number
JPH02106922A
JPH02106922A JP63261831A JP26183188A JPH02106922A JP H02106922 A JPH02106922 A JP H02106922A JP 63261831 A JP63261831 A JP 63261831A JP 26183188 A JP26183188 A JP 26183188A JP H02106922 A JPH02106922 A JP H02106922A
Authority
JP
Japan
Prior art keywords
film
partial pressure
substrate
gas partial
substrate temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63261831A
Other languages
Japanese (ja)
Other versions
JP2647927B2 (en
Inventor
Houki Michimori
方紀 道盛
Junichi Sano
純一 佐野
Kiyoshi Yoneda
清 米田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP63261831A priority Critical patent/JP2647927B2/en
Publication of JPH02106922A publication Critical patent/JPH02106922A/en
Application granted granted Critical
Publication of JP2647927B2 publication Critical patent/JP2647927B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To epitaxially grow a single crystalline Si film on an exposed single crystalline Si substrate by vapor growth under reduced pressure at SiH4 gas partial pressure at a substrate temperature of a range of higher temperature from a predetermined boundary line by means of thermal decomposition of SiH4. CONSTITUTION:A reduced pressure vapor growth is conducted by means of thermal decomposition of SiH4 at a substrate temperature and SiH4 gas partial pressure of a range of higher temperature from a boundary line set at a line passing two points of a point of 20mTorr of SiH4 gas partial pressure at 890 deg.C of substrate temperature and a point of 20mTorr of SiH4 gas partial pressure at 950 deg.C of substrate temperature in which the substrate temperature is at an abscissa axis and the SiH4 gas partial pressure is at an ordinate axis. The substrate temperature and the SiH4 gas partial pressure are set in such a range. Thus, an Si film 8 is not grown on an insulating film 2, and a single crystalline Si film 3 is epitaxially grown only on the single crystalline Si substrate exposed through an opening 2a.

Description

【発明の詳細な説明】 イ)産業上の利用分野 本発明は選択的に5IOz膜を形成した単結晶・Si基
板上に、5I02膜のない84基板表面が露出している
部分上へのみに選択的に単結晶Si膜を成長させる選択
的エピタキシャル成長方法に間する。
DETAILED DESCRIPTION OF THE INVENTION A) Industrial Application Field The present invention is applied to a single crystal Si substrate on which a 5IOz film is selectively formed, only on the exposed part of the 84 substrate surface where the 5IOz film is not formed. A selective epitaxial growth method for selectively growing a single crystal Si film is used.

口) 従来の技術 絶縁R(絶縁物の基板も含む)上に単結晶Si層を形成
したものは、S OI (Silicon on In
5ulat。
Conventional technology The one in which a single-crystal Si layer is formed on an insulator R (including an insulator substrate) is SOI (Silicon on In).
5 ulat.

r)構造と称され、狭い領域で容易に素子分離が行なえ
、高集積化や高速化が可能なものとして知られている。
r) structure, and is known as a structure that allows easy isolation of elements in a narrow area and allows for higher integration and higher speed.

そしと、従来のSi基板上に素子が作製される半導体集
積回路(fc)に比べて、特性向上が図れることから盛
んに研究開発が行なわれている。
As compared to conventional semiconductor integrated circuits (FC) in which elements are fabricated on a Si substrate, research and development are being actively conducted on this because it offers improved characteristics.

絶R層上に単結晶Si膜を形成させるものとして、同相
エピタキシャル成長法があり、これは、単結晶81基板
上に、S!基板面の一部をシードとして露出させて絶縁
膜を形成し、シードと絶縁膜上に非晶質S 、I (以
下a−94と称す)膜を堆積し、600℃程度の低温で
アニールすることで、横方向に同相成長させて、a−8
i膜を米結晶化させるものである。
There is an in-phase epitaxial growth method to form a single crystal Si film on the absolute R layer, and this method is used to form a single crystal Si film on the single crystal 81 substrate. A part of the substrate surface is exposed as a seed to form an insulating film, an amorphous S, I (hereinafter referred to as a-94) film is deposited on the seed and the insulating film, and annealed at a low temperature of about 600°C. By doing so, the in-phase growth in the lateral direction results in a-8
This is to crystallize the i-film.

しかし、この同相成長では、<100>方向の横方向に
優先的にa−3t膜の事納晶化が進むので、横方向の成
長より先にシードから上への縦方向の成長を必要とする
固相エピタキシャル成長では、シード上のa−5ill
[を厚くすることができず、このため、シードと絶縁膜
表面との段差をあまり大きくとることができない。
However, in this in-phase growth, crystallization of the a-3T film preferentially progresses in the lateral direction in the <100> direction, so vertical growth from the seed upwards is required before lateral growth. In solid phase epitaxial growth, a-5ill on the seed
Therefore, it is not possible to make the step between the seed and the surface of the insulating film very large.

ところが、a−3i膜が薄い場合に5シードと絶縁膜表
面との段差が大きいく絶縁膜が厚い)と、堆積されるa
−5i膜に絶縁膜とシードの境の部分で段切れが生じた
り、段切れが生じなくても段差部分での内部応力が大き
くなるため、横方向の同相成長はほとんど起きないか、
起きても横方向成長距離はわずかとなる。
However, if the a-3i film is thin and the step difference between the 5 seed and the insulating film surface is large (the insulating film is thick), the deposited a
In the -5i film, a step break occurs at the boundary between the insulating film and the seed, or even if a step break does not occur, internal stress increases at the step part, so lateral in-phase growth hardly occurs.
Even if it occurs, the lateral growth distance will be small.

このため、シードと絶縁膜表面との段差は出来る限り小
さく、即ち絶縁膜を薄くする必要があり、通常1000
Å以下に形成される。
For this reason, it is necessary to make the level difference between the seed and the surface of the insulating film as small as possible, that is, to make the insulating film thinner.
Formed below Å.

しかしながら、Sol構造を積層した三次元回路素子を
構成する場合、絶縁膜層下にデバイスを形成することに
なるので、デバイス構造や配線および電気的特性の安定
化のための保護を勘案すると、絶縁膜としてIAIa以
上の膜厚が必要になる。
However, when configuring a three-dimensional circuit element with a stacked Sol structure, the device is formed under an insulating film layer, so when considering protection to stabilize the device structure, wiring, and electrical characteristics, it is necessary to The film needs to have a thickness of IAIa or more.

そコテ、例えば’ 5ELECTIVE EPITAX
IAL GROWTtlOF  5ILICON  B
Y  CVD  AND  ITS  丁HERMOD
YNAMICC0N5IDERATIONJ (PRO
CEEDINGS OF THE TENTHINTE
RNATIONAL  C0NFERENCE  ON
  CHEMICAL  VAPORDEPO5ITI
ON 1987. Proceedin@ Vol、8
7−8. PP、379−388>にある様に、選択的
に開孔された5if2膜を形成した単結晶si基板上へ
と、5iHxC12−HCj!−H5(’)常圧CVD
あルイハ減ffCVD法により、常圧の場合950℃乃
至1050℃、減圧の場合850℃乃至950℃の基板
温度で、露出しているSl基板面上のみに単結晶Si膜
を成長きせる!!択的エピタキシャル成長(Selec
tive Epitaxial Gr。
For example, '5ELECTIVE EPITAX
IAL GROWTtlOF 5ILICON B
Y CVD AND ITS DING HERMOD
YNAMICC0N5IDERATIONJ (PRO
CEEDINGS OF THE TENTHINTE
RNATIONAL CONFERENCE ON
CHEMICAL VAPORDEPO5ITI
ON 1987. Procedurein @ Vol, 8
7-8. PP, 379-388>, 5iHxC12-HCj! -H5(') Normal pressure CVD
By using the low-ff CVD method, a single crystal Si film can be grown only on the exposed Sl substrate surface at a substrate temperature of 950°C to 1050°C under normal pressure and 850°C to 950°C under reduced pressure! ! Selective epitaxial growth (Selec)
tive Epitaxial Gr.

wth :以下5EG)法が考えられている。wth (hereinafter referred to as 5EG) method is being considered.

この塩素系ガスを用いたSEG法は、ンラン系ガスの熱
分解による露出している基板面上への単結晶Si膜及び
SfOglI上への多結晶Si膜の堆積と、これら形成
されるSi膜に対するHCffiによるエツチングとを
同時に起こし、エツブング速度が単結晶Si膜よりも多
結晶Sil!lの方が大きいことを利用して、5iov
X上へのSi膜の堆積をなくするものである。
This SEG method using chlorine-based gas involves depositing a single crystal Si film on the exposed substrate surface and a polycrystalline Si film on SfOglI by thermal decomposition of chlorine-based gas, and depositing these formed Si films. At the same time, etching by HCffi occurs simultaneously with polycrystalline Si film, and the etching speed is higher than that of single crystal Si film. Using the fact that l is larger, 5iov
This eliminates the deposition of a Si film on the X.

ハ) 発明が解決しようとする課題 しかし、上述の塩素系ガスを用いたSEG法では、エッ
チャントと考えられるCI!ラジカルが、5i−stポ
ンドあるいは5i−0ポンドを攻撃し切断することでエ
ツチングがなされ、このエツチングにより、堆積した中
、結晶Si膜表面及び多結晶Sl膜表面付近には多数の
欠陥が発生してしまう、また、このSEG法で形成した
Si膜上に更にa−8i膜を堆積させて、このa−81
膜を固相エピタキシャル成長させる場合には、a−5i
膜中に残留するCP原子が混入して結晶化が阻害される
ことになる。そして、横方向の成長距離が短くなり、結
果として大面積のSol構造の基板が得られないことに
なる。
c) Problems to be solved by the invention However, in the SEG method using the above-mentioned chlorine-based gas, CI! which is considered to be an etchant! Etching is performed by radicals attacking and cutting 5i-st pounds or 5i-0 pounds, and as a result of this etching, many defects are generated near the surface of the crystalline Si film and the polycrystalline Sl film in the deposited layer. Furthermore, by further depositing an a-8i film on the Si film formed by this SEG method, this a-81
When growing the film by solid phase epitaxial growth, a-5i
CP atoms remaining in the film will be mixed in and will inhibit crystallization. Then, the lateral growth distance becomes short, and as a result, a substrate with a large area Sol structure cannot be obtained.

更にまた、CVD装置(特に減圧CVD装置)の寿命も
短くなってしまう。
Furthermore, the life of the CVD device (particularly the low pressure CVD device) is also shortened.

本発明は斯様な点に鑑みて為されたもので、塩素ガスを
用いずに、露出している単結晶St基板上へのみに単結
晶Si膜をエピタキシャル成長させるSEG法を提供す
るものである。
The present invention has been made in view of these points, and provides an SEG method for epitaxially growing a single-crystal Si film only on the exposed single-crystal St substrate without using chlorine gas. .

二) 課題を解決するための手段 本発明は、単結晶Si基台上に絶縁膜を形成し、前記単
結晶Si基台表面を露出させる開孔部を前記絶縁膜に形
成し、該絶縁膜に形成された開孔部において露出してい
る前記単結晶Si基台部分にのみ単結晶Si膜をSiH
4の熱分解による減圧気相成長により選択的にエピタキ
シャル成長きせる選択的エピタキシャル成長方法であっ
て、基板温度を横軸に、SiH*ガス分圧を縦軸にとっ
た場合の、基板温度890℃、5i)i4ガス分圧Om
Torrの点と、基板温度950℃、SiHmガス分圧
20mTorrの点の2点を通る線を境界線とし、該境
界線から温度の高い側の範囲の基板温度と51g4ガス
分圧でSiH4の熱分解による減圧気相成長を行うもの
である。
2) Means for Solving the Problems The present invention forms an insulating film on a single-crystal Si base, forms an opening in the insulating film to expose the surface of the single-crystal Si base, and A single-crystal Si film is formed using SiH only on the single-crystal Si base portion exposed in the opening formed in the
4, which is a selective epitaxial growth method that selectively grows epitaxially by low-pressure vapor phase growth using thermal decomposition, where the horizontal axis is the substrate temperature and the vertical axis is the SiH* gas partial pressure, the substrate temperature is 890°C, 5i ) i4 gas partial pressure Om
The boundary line is a line passing through the point Torr and the point where the substrate temperature is 950°C and the SiHm gas partial pressure is 20mTorr. This method performs low-pressure vapor phase growth by decomposition.

ホ)作用 もともと、絶縁膜である5ho2表面は、単結晶81表
面に比べて、Stのダングリングボンドが少ないため、
反応中の表面吸着種(Si)が結合するキンクサイトの
数が少なく、5i膜2表面上には結晶Siの核が発生し
にくい、そこで、基台温度を十分高くすると、表面吸着
種の表面泳動が激しくなり、表面吸着種のキンクサイト
への吸着がされにくくなる。また、5(H4ガス分圧を
十分高い真空度にすることで、表面泳動中の表面吸!1
種がキングサイトに吸着する前に排気される可能性が高
くなる。
e) Effect Originally, the 5ho2 surface, which is an insulating film, has fewer dangling bonds of St than the single crystal 81 surface.
The number of kink sites to which surface adsorbed species (Si) bind during reaction is small, and crystalline Si nuclei are difficult to form on the surface of the 5i film 2. Therefore, if the base temperature is raised sufficiently, the surface adsorbed species The migration becomes more intense, making it difficult for surface adsorbed species to adsorb to kink sites. In addition, 5 (by setting the H4 gas partial pressure to a sufficiently high degree of vacuum, surface absorption during surface migration!
It is more likely that the species will be exhausted before being adsorbed to kingsite.

而して、基台温度とSiH4ガス分圧を上述の如き範囲
内にすることにより、絶縁膜上にはSi膜が成長せず、
開孔部から露出している単結晶St基台上のみに単結晶
Si膜がエピタキシャル成長される。
By keeping the base temperature and SiH4 gas partial pressure within the ranges mentioned above, no Si film will grow on the insulating film.
A single crystal Si film is epitaxially grown only on the single crystal St base exposed through the opening.

へ) 実施例 第1図A乃至Gは本発明一実施例の概略工程図を示す0
本実施例では単結晶Si基台として、単結晶51基板を
用いているが、基板上に形成された単結晶S(膜を用い
ても良い。
Embodiment 1 Figures A to G show a schematic process diagram of an embodiment of the present invention.
In this embodiment, a single crystal 51 substrate is used as the single crystal Si base, but a single crystal S (film) formed on the substrate may also be used.

(1)は(100)面を主面とする単結晶81基台とし
ての単結晶81基板で、その表面に絶縁膜として膜厚I
N4程の5ift膜(2)を熱間変化により形成する(
第1図A)、そしと、この5102膜(2)を、公知の
技術であるフォトリングラフィ技術により、シードとし
てのSi基板表面を露出させる開孔部(2a)を選択的
に形成する(第1図B)。
(1) is a single crystal 81 substrate as a single crystal 81 base with the (100) plane as the main surface, and a film thickness of I as an insulating film on the surface.
A 5ift film (2) of about N4 is formed by hot change (
In FIG. 1A), this 5102 film (2) is then selectively formed with openings (2a) that expose the surface of the Si substrate as a seed using a well-known photolithography technique ( Figure 1B).

次に、このパターン形成された5I02膜(2)を有す
る基板を、I X 10−@taTorr以下の真空中
で赤外線ランプにより940℃まで昇温加熱し、温度を
一定とした後、流量150cc/++ inでArガス
を導入して、Ar圧力65mTorrにしてArスパッ
タを行い、基板表面のクリーニングを5分間行う(第1
図C)、このとき、例えばRF周波数は13.56MH
21出力50Wで、基板には−toovの直流バイアス
を印加しておく。
Next, the substrate having the patterned 5I02 film (2) was heated to 940°C with an infrared lamp in a vacuum below IX10-@taTorr, and after keeping the temperature constant, a flow rate of 150cc/ ++ Introduce Ar gas at 65 mTorr, perform Ar sputtering, and clean the substrate surface for 5 minutes (first
Figure C), at this time, for example, the RF frequency is 13.56MH
21 output of 50 W and a DC bias of -toov was applied to the substrate.

表面のクリーニングが終ったら、基板温度を940°C
に保ったまま、Arガスの供給を止め、RFと直流バイ
アスを切って、5iHnガスを流量4 sccm圧力(
分圧>13mTorrで供給し、開孔部(28)から露
出しているSl基板表面(シード部(1a))上にのみ
、単結晶S(膜(3)を選択的にエピタキシャル成長さ
せる。この単結晶Si膜(3)は、5i02膜(2)と
同じ膜厚まで成長させる(第1図D)。
After cleaning the surface, increase the substrate temperature to 940°C.
While keeping the temperature at
A partial pressure of >13 mTorr is supplied to selectively epitaxially grow a single crystal S (film (3)) only on the surface of the Sl substrate (seed part (1a)) exposed through the opening (28). The crystalline Si film (3) is grown to the same thickness as the 5i02 film (2) (FIG. 1D).

統いて、選択的エピタキシャル成長を行った気相成長装
置の反応室内に設置したまま、SiH4ガスの供給を止
め、I X 101mTorr以下の真空中で、基板温
度を550℃まで低下させた後、再びArガスを流t5
00cc/m1ll、 A r分圧200mTorrに
供給して、13.56MHzのRFを出カフ0Wで印加
し、基板に一60Vの直流バイアスを掛けてArスパッ
タによる基板表面のクリーニングを10分間行う(第1
図E)。
Then, the supply of SiH4 gas was stopped and the substrate temperature was lowered to 550°C in a vacuum of less than I x 101 mTorr while the substrate was placed in the reaction chamber of the vapor phase growth apparatus that performed selective epitaxial growth. Flow the gas t5
00 cc/ml, Ar partial pressure of 200 mTorr was applied, 13.56 MHz RF was applied at output cuff 0 W, a DC bias of -60 V was applied to the substrate, and the substrate surface was cleaned by Ar sputtering for 10 minutes. 1
Figure E).

そして、表面のクリーニングが終ったら、基板温度を5
50℃に保った状態で、Arガスの供給を停止し、RF
と直流バイアスを切ってから、反応室内に5fH4ガス
を流量200sccm、分圧6〈乃至7 )Torrで
供給して、基板表面上に1−8i膜(4)を6000人
(成長速度200人7sin)の厚さに堆積さける(第
1図F)。
After cleaning the surface, lower the substrate temperature to 5.
While maintaining the temperature at 50°C, the supply of Ar gas was stopped and the RF
After turning off the DC bias, 5fH4 gas was supplied into the reaction chamber at a flow rate of 200 sccm and a partial pressure of 6 to 7 Torr to form a 1-8i film (4) on the substrate surface at a growth rate of 6,000 layers (growth rate of 200 tons and 7 sins). ) (Fig. 1F).

その後、反応室内にArガスを導入して残留するSiH
aガスを排気したら、真空引きを行い、室温まで基板温
度を下げる。そして、アニール装置を用いて、大気圧N
堂雰囲気中で600℃の温度での12時間のアニール処
理により、5i−8i膜(4)の固相エピタキシャル成
長を行い、該a−5i IN(4>を単結晶化させた単
結晶Si膜(4′)を得るく第1mG)。
After that, Ar gas is introduced into the reaction chamber to remove the remaining SiH
After exhausting the a gas, perform vacuuming and lower the substrate temperature to room temperature. Then, using an annealing device, atmospheric pressure N
A 5i-8i film (4) was solid-phase epitaxially grown by annealing at a temperature of 600°C for 12 hours in a chamber atmosphere, and a single-crystal Si film ( 4') to obtain the first mG).

さて、第1図りに示す工程においてSEGが行われるわ
けだが、a−81膜(4)を堆積きせる単結晶Si膜(
3)表面に欠陥が多いと、a−51膜のアニールを始め
てから同相成長が起こるまでの遅れ時間が長くなり、*
−9i膜の横方向のエピタキシャル成長距離は短くなっ
てしまう、また、5ift膜(2)上に多結晶S(の核
が発生すると、エピタキシャル成長を阻止する多結晶核
が早く発生するので、やはりa−8i膜の横方向のエピ
タキシャル成長距離は短くなる。従って、第1図りの工
程では良好にSEGを行う必要がある。
Now, SEG is performed in the step shown in the first diagram, and the single crystal Si film (
3) If there are many defects on the surface, the delay time from the start of annealing of the A-51 film to the occurrence of in-phase growth will be longer, *
The epitaxial growth distance in the lateral direction of the -9i film becomes shorter.Also, if polycrystalline S (nuclei) is generated on the 5ift film (2), polycrystalline nuclei that inhibit epitaxial growth are generated quickly. The epitaxial growth distance in the lateral direction of the 8i film becomes short.Therefore, it is necessary to perform SEG well in the step of the first diagram.

第2図はSEGが起きるときと起きないときの基板温度
とSiH4ガス分圧の関係を示す図である。白丸は、S
+基板上にのみRLvJ晶Si模がエピタキシャル成長
し、5iOz膜上にはSi膜が堆積しない場合(即ちS
EGが起きる〉を示し、黒丸は51基板上に東結晶Si
膜がエピタキシャル成長し、5iOz膜上にもS(膜が
堆積する場合く即ちSEGが起きない)を示している。
FIG. 2 is a diagram showing the relationship between substrate temperature and SiH4 gas partial pressure when SEG occurs and when SEG does not occur. The white circle is S
+ When the RLvJ crystal Si pattern is epitaxially grown only on the substrate and no Si film is deposited on the 5iOz film (i.e., S
EG occurs〉, black circles indicate Tokyu crystal Si on the 51 substrate.
The film is epitaxially grown and shows S (when the film is deposited, ie, SEG does not occur) even on the 5iOz film.

第2図から明らかな如く、基台温度を横軸に、S i 
Haガス分圧をt#軸にとり、基板温度890℃、Si
H4ガス分圧O1!Torrの点aと、基板温度950
℃、SiH4ガス分圧20mTorrの点すの2点を通
る線を境界線とし、この境界線から温度の高い側の範囲
の基板温度とSiH4ガス分圧に設定して減圧気相成長
させたときにのみSEGが実現される。
As is clear from Fig. 2, with the base temperature on the horizontal axis, S i
The Ha gas partial pressure is taken on the t# axis, the substrate temperature is 890°C, and the Si
H4 gas partial pressure O1! Torr point a and substrate temperature 950
℃, SiH4 gas partial pressure 20 mTorr, and the line passing through the two points is taken as a boundary line, and when the substrate temperature and SiH4 gas partial pressure are set in the higher temperature range from this boundary line, low pressure vapor phase growth is performed. SEG is realized only in

これは、基台温度を十分高くすると、表面吸着種の表面
泳動が激しくなり、表面吸着種のキンク−サイトへの吸
着がきれにくくなり、また、SiH4ガス分圧を十分高
い真空度にすることで、表面泳動中の表面吸着種がキン
グサイトに吸着する前に排気される可能性が高くなる。
This is because if the base temperature is raised sufficiently, the surface migration of the surface adsorbed species will be intense, making it difficult for the surface adsorbed species to adsorb to the kink site, and if the SiH4 gas partial pressure is raised to a sufficiently high degree of vacuum. Therefore, there is a high possibility that the surface-adsorbed species during surface migration will be exhausted before being adsorbed to kingsite.

而して、基台温度とSiH<ガス分圧を第2図に斜線で
示す範囲に設定することにより、Sh。
By setting the base temperature and SiH<gas partial pressure in the range shown by diagonal lines in FIG. 2, Sh.

2膜上にはSi膜は堆積せずに単結晶Si基板−ヒにの
みのSi膜の堆積がされ、即ちSEGが行われる。
No Si film is deposited on the two films, and a Si film is deposited only on the single crystal Si substrate, that is, SEG is performed.

ト) 発明の効果 本発明は以上の説明から明らかな如く、基板温度5iH
hガス分圧を制御することで、塩素ガスを用いずにSE
Gを行うことができる。従って、固相エピタキシャル成
長させるためのシードとなる単結晶Si膜に欠陥が発生
するのを抑制し、またa−5i膜中に不純物が混入する
機会を減らすことができる。その結果、a−5l膜を同
相エピタキシャル成長させるときに、横方向への成長距
離を伸ばすことができ:大面積のSOI構造の基板を提
供することが可能となる。
g) Effects of the Invention As is clear from the above description, the present invention has a substrate temperature of 5iH.
h By controlling the gas partial pressure, SE can be performed without using chlorine gas.
G can be done. Therefore, it is possible to suppress the occurrence of defects in the single crystal Si film that serves as a seed for solid phase epitaxial growth, and to reduce the chance of impurities being mixed into the a-5i film. As a result, when growing the a-5l film by in-phase epitaxial growth, the lateral growth distance can be extended, and it is possible to provide a substrate with a large area SOI structure.

また、塩素ガスを用いないので減圧CVD装置等の成長
装置の寿命を長くすることに寄与きれる。
Furthermore, since chlorine gas is not used, it can contribute to extending the life of growth equipment such as low pressure CVD equipment.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図A乃至Gは本発明一実施例の工程説明図、第2図
はSEGを実現するための条件を示1図である。 (1)・・・単結晶Si基板、(la)・・・シード、
(2)・・・5i02膜(絶縁膜)、(2a)・・・開
孔部、(3〉・・・単結晶S目L(4)・・・a−Sl
膜、(4′)・・・単結晶S(膜。 第1図
1A to 1G are process explanatory diagrams of an embodiment of the present invention, and FIG. 2 is a diagram showing conditions for realizing SEG. (1)...Single crystal Si substrate, (la)...Seed,
(2)...5i02 film (insulating film), (2a)...opening part, (3>...single crystal S eye L(4)...a-Sl
Film, (4')...Single crystal S (film. Figure 1

Claims (1)

【特許請求の範囲】 1)単結晶Si基台上に絶縁膜を形成し、前記単結晶S
i基台表面を露出させる開孔部を前記絶縁膜に形成し、
該絶縁膜に形成された開孔部において露出している前記
単結晶Si基台部分にのみ単結晶Si膜をSiH_4の
熱分解による減圧気相成長により選択的にエピタキシャ
ル成長させる選択的エピタキシャル成長方法において、 基台温度を横軸に、SiH_4ガス分圧を縦軸にとった
場合の、基板温度890℃、SiH_4ガス分圧0mT
orrの点と、基板温度950℃、SiH_4ガス分圧
20mTorrの点の2点を通る線を境界線とし、該境
界線から温度の高い側の範囲の基板温度とSiH_4ガ
ス分圧でSiH_4の熱分解による減圧気相成長を行う
ことを特徴とする選択的エピタキシャル成長方法。
[Claims] 1) An insulating film is formed on a single-crystal Si base, and the single-crystal S
i forming an opening in the insulating film that exposes the surface of the base;
In a selective epitaxial growth method, a single crystal Si film is selectively epitaxially grown only on the single crystal Si base portion exposed in the opening formed in the insulating film by low pressure vapor phase growth using thermal decomposition of SiH_4, When the horizontal axis is the base temperature and the vertical axis is the SiH_4 gas partial pressure, the substrate temperature is 890°C and the SiH_4 gas partial pressure is 0 mT.
The boundary line is a line passing through the point of orr and the point where the substrate temperature is 950°C and the SiH_4 gas partial pressure is 20 mTorr. A selective epitaxial growth method characterized by performing low pressure vapor phase growth by decomposition.
JP63261831A 1988-10-17 1988-10-17 Selective epitaxial growth method Expired - Fee Related JP2647927B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63261831A JP2647927B2 (en) 1988-10-17 1988-10-17 Selective epitaxial growth method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63261831A JP2647927B2 (en) 1988-10-17 1988-10-17 Selective epitaxial growth method

Publications (2)

Publication Number Publication Date
JPH02106922A true JPH02106922A (en) 1990-04-19
JP2647927B2 JP2647927B2 (en) 1997-08-27

Family

ID=17367343

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63261831A Expired - Fee Related JP2647927B2 (en) 1988-10-17 1988-10-17 Selective epitaxial growth method

Country Status (1)

Country Link
JP (1) JP2647927B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0474415A (en) * 1990-07-17 1992-03-09 Nec Corp Selective epitaxial growth method of silicon
US5221412A (en) * 1989-09-26 1993-06-22 Toagosei Chemical Industry Co., Ltd. Vapor-phase epitaxial growth process by a hydrogen pretreatment step followed by decomposition of disilane to form monocrystalline Si film
US5441012A (en) * 1990-09-21 1995-08-15 Anelva Corporation Thin film deposition method for wafer
US6319782B1 (en) 1998-09-10 2001-11-20 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of fabricating the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5221412A (en) * 1989-09-26 1993-06-22 Toagosei Chemical Industry Co., Ltd. Vapor-phase epitaxial growth process by a hydrogen pretreatment step followed by decomposition of disilane to form monocrystalline Si film
JPH0474415A (en) * 1990-07-17 1992-03-09 Nec Corp Selective epitaxial growth method of silicon
US5441012A (en) * 1990-09-21 1995-08-15 Anelva Corporation Thin film deposition method for wafer
US6319782B1 (en) 1998-09-10 2001-11-20 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of fabricating the same
US6906382B2 (en) 1998-09-10 2005-06-14 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of fabricating the same

Also Published As

Publication number Publication date
JP2647927B2 (en) 1997-08-27

Similar Documents

Publication Publication Date Title
US5037774A (en) Process for the production of semiconductor devices utilizing multi-step deposition and recrystallization of amorphous silicon
JPH076950A (en) Method of making structural parts for electronic, lightning and optical components
JPH02191320A (en) Crystal product and its manufacture
JP3220864B2 (en) Method for manufacturing semiconductor device
JP2647927B2 (en) Selective epitaxial growth method
US8329532B2 (en) Process for the simultaneous deposition of crystalline and amorphous layers with doping
JP3157280B2 (en) Method for manufacturing semiconductor device
JP2771636B2 (en) Selective epitaxial growth method
JPH02191319A (en) Method of forming soi structure
JPH0258217A (en) Metallic film forming method
JP2961188B2 (en) Method for manufacturing SOI substrate
JP2755653B2 (en) Method of forming SOI structure
JPH0216720A (en) Solid phase epitaxy method
JPH0529214A (en) Method for manufacturing semiconductor substrate
JP3541332B2 (en) Method for manufacturing semiconductor device
JP3112796B2 (en) Chemical vapor deposition method
JPH01152719A (en) Formation of soi structure
JP3968222B2 (en) Method for forming semiconductor thin film
JPH05217889A (en) Manufacture of semiconductor device
JPH0758692B2 (en) Method for manufacturing semiconductor device
JPH05259103A (en) Pretreatment method for forming metal for wiring
JPH05234886A (en) Method for manufacturing semiconductor device
JPH02208920A (en) Soi structure forming method
JPH03101121A (en) Formation of soi structure
JPH01125955A (en) Formation of wiring of semiconductor device

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees