JPH02106937A - Semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture a hetero-bipolar transistor with high yield by forming a base region composed of an SiGe layer shaped into a specified region on one surface of an Si substrate and a lower base connected to the underside of the peripheral section of the base region. CONSTITUTION:An n<+> buried layer 12 as a collector contact and an n-type Si layer 13 as a collector are shaped in a specified region demarcated by an isolation insulating layer 11. An external base 14 into which a p-type impurity is introduced through a thermal diffusion or ion implantation is formed in the predetermined region of the Si layer 13. A p-type SiGe layer 15 as a base is shaped onto the Si layer 13 so that its a peripheral section is superposed on the external base 14, and an n-type Si layer 16 As an emitter is formed onto the SiGe layer 15. An inter-layer insulating layer 17 is shaped onto the whole surface on an Si substrate 10, and metallic electrodes 18 connected to the Si layer 13, the external base 14, and the Si layer 16 are formed separately from openings bored at the specified locations of the inter-layer insulating layer 17, thus constituting a hetero-bipolar transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION [(Already Required)] Regarding a heterobipolar transistor (IIBT) having a base made of a 5iGe layer.

5 formed in a predetermined area on one surface of the St substrate (10) for the purpose of manufacturing a hetero bipolar transistor having a low resistance external base with high yield.
It has a base region made of an iGe layer (15), and an external base (14) provided on the surface of the substrate and connected to the lower surface of the periphery of the base region.

[Industrial application field]

The present invention provides a hetero bipolar transistor (H) having a base layer made of silicon germanium (SiGe).
Regarding BT).

[Conventional technology]

Hetero-bipolar transistors have a high current amplification factor (h,
), and high-speed operation is possible because the large resistance can be reduced.

Recently, a heterobipolar transistor based on a 5iGe layer epitaxially grown on a silicon (Si) substrate has been proposed. (S, S, ↑Ver+ eta
IEDM Tech, Dig, lpp, 3
25-354.1987) According to this configuration, it is possible to manufacture a hetero bipolar transistor based on established silicon integrated circuit technology, and it is expected to promote the practical use of hetero bipolar transistors.

[Problem to be solved by the invention]

The general structure of the above-mentioned hetero bipolar transistor (HBT") is as shown in the cross-sectional view of FIG. The 5iGe layer 2 is patterned so that a part thereof becomes the external base 4. In FIG. 1, 5 is an insulating layer, and 6 and 7 are
are electrodes connected to the external base 4 and the 54 layer 3 through openings provided at predetermined positions in the insulating layer 5, respectively.

However, the thickness of the 5iGe layer that can be epitaxially grown with good crystallinity on the Si substrate 1 is at most 400 nm.
It's a person. As a result, the external base 4 has a small thickness;
The resistance value increases. In addition, it is difficult to detect the end point when etching the 5iGe layer 2 by several hundred layers so that the external base 4 remains, and not only does the thickness of the external base 4 easily fluctuate, but also the entire external base 4 is etched. There were problems such as it being difficult to obtain a high yield due to the defects that occur.

An object of the present invention is to make it possible to manufacture a hetero-bipolar transistor having a low-resistance external base at a high yield by not forming an external base with a 5iGe layer serving as a base as in the conventional structure.

[Means to solve the problem]

The above object includes a base region made of a 5iGe layer (15) formed in a predetermined area on one surface of a Si substrate (10), and an external base provided on the surface of the substrate and connected to the lower surface of the periphery of the base region. (14) This is achieved by the hetero bipolar transistor according to the present invention, which is characterized by having the following.

[For production]

Before forming the 5rGe layer serving as the base, p-type impurities are introduced into the periphery of a predetermined region defined on the substrate surface so as to overlap with the periphery of the region.

Alternatively, an external base is formed by depositing a polycrystalline silicon layer doped with p-type impurities.

Thereafter, a 5iGe layer and a Si layer constituting the emitter are grown. Then, patterning is performed so that the 5iGe layer and the Si layer remain only within the predetermined region. According to this structure, the thickness of the external base can be controlled independently of the thickness of the 5iGe layer serving as the base. As a result, the resistance value of the external base can be reduced and therefore 5iGe
The operating speed of layer-based HBTs can be increased. In addition, the end point of etching for forming the 8 external base is reliably detected, and the manufacturing yield of the 118T can be improved.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a main part showing an embodiment of the present invention,
A separation insulating layer 11 is formed on the Si substrate 10.
In a predetermined area defined by the isolation insulating layer 11, a buried layer 12 serving as a collector contact and an n buried layer 12 serving as a collector are provided.
A type Si layer 13 is formed. An external base 14 into which p-type impurities are introduced by thermal diffusion or ion implantation is formed in a predetermined region of the St layer 13. and,
A p-type 5iGe layer 15 serving as a base is formed on the 31st layer 13 so that its peripheral portion overlaps with the external base 14, and further on the 5iGe layer 15 is an n-type Si layer 15 serving as an emitter. A layer 16 is formed. Furthermore, 5
The thicknesses of iGe layer 15 and St layer 16 are about 400 and about 3000, respectively.

Furthermore, the p-type impurity concentration in the external base 14 is as follows.

For example, lXl014 atoms/CII+2.

A glabellar insulating layer 17 made of SiO□, for example, is formed on the entire surface of the Si substrate 10, and the Si layer 13. External base 14. A metal electrode 18 connected to the Si layer 16 is formed to constitute a hetero bipolar transistor.

According to the structure of the present invention, the resistance value of the external base 14 is determined by the size and impurity concentration of the region into which the p-type impurity is introduced, regardless of the thickness of the 5iGe layer 15.

Therefore, it is possible to reduce the resistance value of the external base 4 in the conventional structure shown in FIG. In addition, since there is no need to leave the 5iGe layer 15 as an external base, the 5i
End point detection in etching for patterning the Ge layer 15 and Si layer 16 can be performed reliably and easily by exposing the external base 14. Furthermore, the depth of the impurity diffusion layer constituting the external base 14 is increased by several thousand.
It is easy to control Ce to a human level, and even if the surface of the external base 14 is etched to some extent in the etching process, there is no substantial problem with the external base resistance value.

FIG. 2 is a cross-sectional view for explaining the main part of the manufacturing process of the hetero-bipolar transistor (I(BT)) having the structure of the present invention shown in FIG.

Referring to FIG. 2(a), although not shown in FIG. 2, the separation insulating layer 11. n” buried layer 12.
An n-type 81 layer 13 is formed. A resist layer 20 having an opening 21 corresponding to the external base 14 is made of Si-based Fi.
The silicon substrate 10 is formed on a Si substrate 10 using the resist layer 20 as a mask, and ions such as boron (B) are implanted into the Si substrate 10. An example of this ion implantation condition is that the ion acceleration energy is 30 KeV.
.

The dose amount is lXl0'' atoms/cII+2. Accordingly.

A p-type impurity region 22 is formed. Note that after providing a mask made of an SiO□ film instead of the resist layer 20, a BSG (borosilicate glass) film is provided on the entire surface of the Si substrate 10, and heat treatment is performed to selectively diffuse boron in the BSG into the Si substrate 1o. The external base 14 may be formed thereby.

After the above, the resist 120 is removed, and then.

The Si substrate IO is annealed at 900° C. for 30 minutes in a N2 gas atmosphere. Boron (B) ion-implanted by this
is activated, and the p-type impurity region 22 is connected to the external base 1.
It becomes 4. Next, the Si substrate 10 is placed in a rapid thermal epitaxial growth apparatus using, for example, an infrared lamp heating method, and SiH4 and GeH as growth source gases and B2H6 as a doping source gas are introduced into this epitaxial growth apparatus to form the St substrate l.
A p-type 5iGe layer 15 with a thickness of about 400 nm is epitaxially grown on the O2 layer. The p-type impurity concentration in the 5iGe layer I5 is approximately 7×10" atoms/c112. In this case, the composition ratio in the 5iGeji15 is 1 based on the design value of the current amplification factor of the hetero bipolar transistor.
For example, it can be determined to be Si:Ge.8:2. Next, the growth source gas SiH4 and A s as the doping source gas
! + 3 to a thickness of approximately 30 nm on the 5iGe layer 15.
An n-type Si layer 16 of 0.000 nm is epitaxially grown.

The n-type impurity concentration in 5ii16 is lXl0'' atoms/
It should be about c1112. This state is shown in FIG. 2 (bl).The 5iGe layer 15 and Si layer 1G in the above
Needless to say, a vapor phase growth method such as MBE can be used for the growth.

After the above, as shown in FIG. 2(C), a resist layer 23 whose peripheral portion overlaps with the external base I4 is formed on the 5iN 16, and using the resist layer 23 as a mask, the exposed Si layer 16 and 5iGe are Remove layer 15. This removal can be carried out by the RIB method using a mixed gas of, for example, C1 and CCt as an etching agent.

As a result, a mesa-shaped 5i was formed in a predetermined area on the Si substrate IO.
Ge layers 15 and 5iji 16 are formed. In addition, the above R
At fH, the Si substrate 10 around the mesa-shaped 5iGe layer 15 etc. is slightly removed and the 5iGe layer 15 is removed as shown in Figure 9.
There is no problem in forming a mesa-shaped Si substrate 10 under the layer 15, or as shown in FIG. 2 (d+).

There is no problem even if a thin 5iGe layer remains around the mesa-shaped 5iGeji15.

Thereafter, an interlayer insulating layer 17 and a metal electrode 18 as shown in FIG. 1 are formed to complete the hetero bipolar transistor of the present invention.

Figure 3 shows a hetero bipolar transistor (H) of the present invention.
FIG. 3 is a cross-sectional view of main parts showing another example of the structure of BT. This embodiment utilizes the well-known 5rcos technology, in which an isolation insulating layer 11゜n゛ is buried in a Si substrate 10.
and n-type 5iN13 are formed.

In a bipolar transistor with 5ICOS structure.

A p-type Si layer 13' is formed on top of the n-type T layer 13 in contact with a polycrystalline silicon layer 25 serving as an external base electrode, and this constitutes a base. ' is n-type and is formed integrally with the 81 layer 13. Similar to the 5rcos structure, the polycrystalline silicon layer 25 is doped with p-type impurities.

As a result, this p-type impurity is diffused into the Si layer I3.
'pff area 26 is formed.

After a p-type 5iGe layer and an n-type Si layer having the same thickness and impurity concentration as in the previous example were sequentially grown on the Sii plate IO surface on which the polycrystalline silicon layer 25 was formed, these layers were By selectively etching, as shown in Figure 1, a p-type 5iGe layer 15 serving as a base and an n-type Si layer 16 serving as an emitter are formed. p-type 5iG
The e layer 15 is patterned so that its peripheral portion is in contact with the p'' region 26. Hereafter.

Similar to the above embodiment, an interlayer insulating layer 1 is formed on the Si substrate IO.
7 and metal electrode 18 are formed to complete a hetero bipolar transistor having the structure of the present invention.

FIG. 4 shows the hetero bipolar transistor (II) of the present invention.
FIG. 4 is a sectional view of a main part showing still another example of the structure of BT. Similar to the previous embodiment, the Si substrate 10 has an n° buried layer 12. An n-type Si layer 13 and an isolation insulating layer 11 are formed. In the structure of this embodiment, nine isolation insulating layers 11
An external base 27 made of, for example, a polycrystalline silicon layer is formed on the top 1. On the Si substrate 10.

p-type 5iGe so that its periphery is in contact with the external base 27.
A layer 15 is formed, and an n-type Si layer 16 is formed on the 5iGe layer 15. External base 27 is doped with p-type impurities. The thickness and impurity concentration of the 5iGe layer 15 and the Si layer 16 are the same as in the previous example, and they are patterned using the same mask as in the previous example. Furthermore, an insulating layer 17 and a metal electrode 18
A hetero bipolar transistor having the structure of the present invention is completed.

〔Effect of the invention〕

According to the present invention, in a hetero bipolar transistor based on a 5iGe layer, the external base resistance can be reduced and the operating speed can be improved. Furthermore, there is no need to leave the 5iGe layer constituting the base in the external base region (this makes it easy to detect the end point of etching when patterning the 5iGe layer into the shape of the base).
This has the effect of improving manufacturing yield.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a main part showing an embodiment of an I(BT) having a structure of the present invention. FIG. 4 and 4 are sectional views of main parts showing different embodiments of I(BT) having the structure of the present invention. FIG. 5 is a sectional view of main parts showing the general structure of a conventional HBT. 10 is a Si substrate. 11 is a separation insulating layer. 12 is a buried layer. 13 and 16 are Si layers 14 and an external base 15 is a 5iGe layer. 17 is an interlayer insulating layer 18 is a metal electrode. 20 and 23 are resist layers. 21 22 is an opening. 22 is a p-type impurity region. 25 is a polycrystalline silicon layer. 26 is a p'' region 27 is an external base failure FfI Lee Chu Chae's HBT15 drawing showing the drawing of the electric bomb recommendation

Claims (1)

[Claims] A base region made of a silicon germanium layer (15) formed in a predetermined area on one surface of a substrate (10), and a base region formed on the surface of the substrate and connected to the lower surface of the periphery of the base region. A semiconductor device characterized in that it has an external base (14).