JPH02106942A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02106942A
JPH02106942A JP63261820A JP26182088A JPH02106942A JP H02106942 A JPH02106942 A JP H02106942A JP 63261820 A JP63261820 A JP 63261820A JP 26182088 A JP26182088 A JP 26182088A JP H02106942 A JPH02106942 A JP H02106942A
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor element
electrode pad
cleaning
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63261820A
Other languages
Japanese (ja)
Other versions
JP2674144B2 (en
Inventor
Yoshiaki Hisamune
義明 久宗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63261820A priority Critical patent/JP2674144B2/en
Publication of JPH02106942A publication Critical patent/JPH02106942A/en
Application granted granted Critical
Publication of JP2674144B2 publication Critical patent/JP2674144B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/0711Apparatus therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/015Manufacture or treatment of bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/015Manufacture or treatment of bond wires
    • H10W72/01515Forming coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/015Manufacture or treatment of bond wires
    • H10W72/01571Cleaning, e.g. oxide removal or de-smearing
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07511Treating the bonding area before connecting, e.g. by applying flux or cleaning
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造方法に関し、特に半導体素
子の電極パッドと外部導出線とを金属導線で結合した後
に、上記半導体素子表面に保護膜を形成する半導体装置
の製造方法に関する。
Detailed Description of the Invention [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular, after bonding an electrode pad of a semiconductor element and an external lead wire with a metal conducting wire, a protective layer is applied to the surface of the semiconductor element. The present invention relates to a method for manufacturing a semiconductor device in which a film is formed.

〔従来の技術〕[Conventional technology]

一般に、半導体装置は外部からの熱的、化学的および物
理的な影響を受けて、半導体素子の電気的特性の変動等
信頼性上の問題を生じている。特に、樹脂封止型半導体
装置における半導体素子(チップ)の電極パッドと金属
導線(ポンディングワイヤ)との接続部での電極パッド
の腐食が法則な問題を引き起こしている。そのため、半
導体素子の電極パッドと外部導出線(リード)とを金属
導線で結合(ボンディング)した後に、上記半導体素子
表面に400℃以下の低温で絶縁膜を形成し、半導体素
子表面を被覆・保護することを発明者は別に出願した特
許願(例えば、特願昭62−167264.特願昭62
−242113)で提案した。
In general, semiconductor devices are subject to external thermal, chemical, and physical influences, causing reliability problems such as fluctuations in the electrical characteristics of semiconductor elements. In particular, corrosion of electrode pads at the connection portions between electrode pads of semiconductor elements (chips) and metal conductive wires (bonding wires) in resin-sealed semiconductor devices causes regular problems. Therefore, after bonding the electrode pad of the semiconductor element and the external lead wire (lead) with a metal conductor wire, an insulating film is formed on the surface of the semiconductor element at a low temperature of 400 degrees Celsius or less to cover and protect the surface of the semiconductor element. The inventor filed a separate patent application (for example, Japanese Patent Application No. 62-167264.
-242113).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した絶縁膜による被覆保護技術は半導体素子表面が
清浄であって初めて腐食効果をあげることが可能となる
。しかし、実際には半導体装置を製造する際に、半導体
素子表面には種々の不純物が付着する可能性がある。例
えば、半導体素子を製造する拡散工程においては、ドラ
イエツチング等に際して、半導体素子上に形成された電
極Auパッド上に不純物(とくに、フッ素)が残留する
ことがある(例えば、日経マイクロデバイス1986年
1月号、96頁)。あるいは、半導体素子をパッケージ
ングする組立工程においても、様々な不純物による汚染
のあることが報告されている(月間Sewicondu
ctor World  1987年9月263〜69
頁)。そのため、従来の絶縁膜の被覆保護技術は安定し
た防食作用が再現されないという欠点があった。
The coating protection technique using an insulating film described above can only be effective in corroding when the surface of the semiconductor element is clean. However, in reality, when manufacturing a semiconductor device, various impurities may adhere to the surface of the semiconductor element. For example, in the diffusion process for manufacturing semiconductor devices, impurities (especially fluorine) may remain on the electrode Au pads formed on the semiconductor devices during dry etching, etc. (for example, Nikkei Micro Devices 1986, Vol. 1). Monthly issue, page 96). Furthermore, it has been reported that there is contamination by various impurities in the assembly process for packaging semiconductor devices (Monthly Sewicondu
ctor World September 1987 263-69
page). Therefore, the conventional insulating film coating protection technology has the drawback that stable corrosion protection cannot be reproduced.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置の製造方法は、半導体素子の電極パ
ッドと外部導出線とが金属導線により接続された半導体
素子表面を絶縁膜で被覆保護する半導体装置の製造にお
いて、上記絶縁膜の被覆前に半導体素子表面を洗浄する
工程を有している。
The method for manufacturing a semiconductor device of the present invention provides a method for manufacturing a semiconductor device in which a surface of a semiconductor element in which an electrode pad of a semiconductor element and an external lead wire are connected by a metal conducting wire is coated and protected with an insulating film. The method includes a step of cleaning the surface of the semiconductor element.

そして、この洗浄工程としては具体的には、不活性気体
放電により半導体素子表面をスパッタエツチングする方
法、または0.ガス雰囲気において半導体素子表面を晒
す方法等がある。
Specifically, this cleaning step includes a method of sputter etching the surface of the semiconductor element using an inert gas discharge, or a method of sputter etching the surface of the semiconductor element using an inert gas discharge. There are methods such as exposing the surface of the semiconductor element in a gas atmosphere.

本発明は、清浄な半導体素子表面を形成した後に絶縁膜
を形成することによって耐湿性の高い半導体装置を再現
性よく製造できる。
According to the present invention, a semiconductor device with high moisture resistance can be manufactured with good reproducibility by forming an insulating film after forming a clean semiconductor element surface.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は、本発明の第1の実施例に使用したアルゴンス
パッタリング装置の概略図である。101は反応炉、1
02は試料、103は下部電極である。下部電極103
は、ブロッキングコンデンサー104を介して高周波電
源105に接続されている。106は上部電極、107
はアルゴンガス導入管、108は真空排気管である。
FIG. 1 is a schematic diagram of an argon sputtering apparatus used in a first embodiment of the present invention. 101 is a reactor, 1
02 is a sample, and 103 is a lower electrode. Lower electrode 103
is connected to a high frequency power source 105 via a blocking capacitor 104. 106 is the upper electrode, 107
108 is an argon gas introduction pipe, and 108 is a vacuum exhaust pipe.

スパッタリング装置の反応炉101の中の下部電極10
3上に試料102を設置し、アルゴンガスを放電させる
ことにより、試料102表面はアルゴンイオンによりス
パッタリングされる。例えば、Arガス圧力を8mTo
rrに保ち、300Wの高周波を印加して形成した放電
アルゴン中に、アルミニウム薄膜を成長した試料を設置
した場合、アルミニウム薄膜は約100人/ m i 
nの速さでエツチングされる。その結果、清浄なアルミ
ニウム表面を1〜2分で得ることが可能である。
Lower electrode 10 in the reactor 101 of the sputtering device
By placing the sample 102 on the sample 3 and discharging argon gas, the surface of the sample 102 is sputtered with argon ions. For example, set the Ar gas pressure to 8mTo
When a sample on which an aluminum thin film was grown is placed in a discharge argon atmosphere formed by applying a high frequency of 300 W while keeping the temperature at
It is etched at a speed of n. As a result, it is possible to obtain a clean aluminum surface in 1-2 minutes.

第2図(a)〜(d)に本発明の第1の実施例の主な工
程を示す。第2図(a)は第1図の反応炉101に入れ
るべき試料102の断面図であり、リードフレーム20
2上に半導体素子(チップ)203がマウントされ、金
線205によりポンディングされている様子を示す。2
01,202はリードフレームであり、201はその外
部導出線(リード)となる部分、202は半導体素子を
マウントする部分である。203は半導体素子(チップ
)であり、204は半導体素子203上に形成されたア
ルミニウム電極パッド、205は保護膜である。また、
206は電極204および外部導出線201を接続する
金線(ポンディングワイヤ)である。
FIGS. 2(a) to 2(d) show the main steps of the first embodiment of the present invention. FIG. 2(a) is a cross-sectional view of the sample 102 to be placed in the reactor 101 of FIG.
A semiconductor element (chip) 203 is mounted on 2 and bonded with a gold wire 205. 2
Reference numerals 01 and 202 are lead frames, 201 is a portion serving as an external lead line (lead), and 202 is a portion for mounting a semiconductor element. 203 is a semiconductor element (chip), 204 is an aluminum electrode pad formed on the semiconductor element 203, and 205 is a protective film. Also,
206 is a gold wire (ponding wire) connecting the electrode 204 and the external lead wire 201.

第2図(b)は、第1図の反応炉101に第2図(a)
に示した試料を入れアルゴンにより表面がスパッタエツ
チングされている状態を示す。図において207は放電
アルゴンを示す。例えば、圧力0.8mTorrのアル
ゴンを300Wの高周波電圧を印加して形成した放電ア
ルゴンに1分間晒すことにより、電極パッド204.保
護膜205.および金線206等の表面を清浄化するこ
とができる。
FIG. 2(b) shows the reactor 101 in FIG. 1 and FIG. 2(a).
This figure shows the sample shown in Fig. 3 being placed and the surface being sputter-etched with argon. In the figure, 207 indicates discharge argon. For example, by exposing argon at a pressure of 0.8 mTorr to discharge argon formed by applying a high frequency voltage of 300 W for 1 minute, the electrode pad 204. Protective film 205. Also, the surfaces of the gold wire 206 and the like can be cleaned.

第2図(c)は、成長温度200〜250℃で化学気相
成長(CVD)により絶縁膜208を半導体素子203
に被覆した様子を示す。絶縁膜208としては、シリコ
ン酸化膜(Sin2)、シリコン窒化膜(SiN)、シ
リコン酸化窒化膜(SiON)が適当である。
FIG. 2(c) shows an insulating film 208 formed on a semiconductor element 203 by chemical vapor deposition (CVD) at a growth temperature of 200 to 250°C.
This shows how it is coated. As the insulating film 208, a silicon oxide film (Sin2), a silicon nitride film (SiN), and a silicon oxynitride film (SiON) are suitable.

最後に、第2図(d)に樹脂封止を行い、リードフレー
ム201を切断・整形し、製品として完成した半導体装
置を示す。ここで、209は封入樹脂である。
Finally, FIG. 2(d) shows a semiconductor device completed as a product by resin sealing, cutting and shaping the lead frame 201. Here, 209 is an encapsulating resin.

一般に、樹脂封止型半導体装置の耐湿不良モードは、半
導体素子203上に形成された金属電極(パッド)20
4の腐食であり、この腐食はイオン性不純物と水分の存
在により著しく加速される。
Generally, the moisture resistance failure mode of a resin-sealed semiconductor device is caused by the metal electrode (pad) 20 formed on the semiconductor element 203.
4, and this corrosion is significantly accelerated by the presence of ionic impurities and moisture.

上記第2図(a)〜(d)に示したように、本発明の半
導体装置の製造方法によれば半導体素子203表面およ
び電極パッド204表面は放電アルゴンにてスパッタエ
ツチングされ清浄な表面が形成され、次いで絶縁膜20
8に被覆・保護されている。
As shown in FIGS. 2(a) to 2(d) above, according to the method of manufacturing a semiconductor device of the present invention, the surface of the semiconductor element 203 and the surface of the electrode pad 204 are sputter-etched with discharge argon to form a clean surface. and then the insulating film 20
8 is covered and protected.

電極パッド204表面は、絶縁膜208で覆われている
ので封入樹脂207とは直接接することなく、常に清浄
である。この結果、耐湿性を飛躍的に向上させた半導体
装置を製造することが可能となる。
Since the surface of the electrode pad 204 is covered with an insulating film 208, it does not come into direct contact with the encapsulating resin 207 and is always clean. As a result, it becomes possible to manufacture a semiconductor device with dramatically improved moisture resistance.

以上の説明からも明らかなように、第2図(b)で示し
た半導体素子203表面の洗浄工程は重要である。その
理由は、半導体素子203表面にイオン性不純物が付着
していたならば、絶縁膜208で半導体素子203表面
および電極パッド204表面を被覆・保護して外部から
の不純物の侵入を防止しても、半導体素子203表面に
付着したイオン性不純物によって電極パッド204の腐
食が進行してしまうためである。
As is clear from the above description, the process of cleaning the surface of the semiconductor element 203 shown in FIG. 2(b) is important. The reason is that if ionic impurities adhere to the surface of the semiconductor element 203, even if the insulating film 208 covers and protects the surface of the semiconductor element 203 and the electrode pad 204 to prevent impurities from entering from the outside. This is because corrosion of the electrode pad 204 progresses due to ionic impurities adhering to the surface of the semiconductor element 203.

通常、電極204表面は、電極パッド204部を含む金
属配線、および電極パッド上の保護膜のドライエツチン
グによるエツチングガスからの不純物汚染が認められて
いる。多くの場合、電極パッド204表面はフッ素炭素
等がオージェ電子分光法により検出されるが、本実施例
のアルゴンスバッタエッチング工程を用いることにより
、これらは全く検出されることが確められた。
Usually, the surface of the electrode 204 is contaminated with impurities from the etching gas due to dry etching of the metal wiring including the electrode pad 204 and the protective film on the electrode pad. In many cases, fluorine carbon and the like are detected on the surface of the electrode pad 204 by Auger electron spectroscopy, but by using the argon sputter etching process of this example, it was confirmed that these were completely detected.

第3図は本発明の第2の実施例に使用したオゾン洗浄装
置の概略図を示す。301は反応炉、302は試料10
2を設置するサセプター 303は試料102を加熱す
るヒータ、304はオゾン導入管、305は排気管であ
る。また、306は酸素ガス供給管、307はオゾン発
生器であり、酸素ガス供給管306から導入された酸素
(02)はオゾン(Ol)に変換され、オゾン導入管3
04に送られる。308は反応を促進するための紫外光
を照射する低圧水銀ランプである。
FIG. 3 shows a schematic diagram of an ozone cleaning device used in a second embodiment of the present invention. 301 is the reactor, 302 is sample 10
303 is a heater for heating the sample 102, 304 is an ozone introduction pipe, and 305 is an exhaust pipe. Further, 306 is an oxygen gas supply pipe, and 307 is an ozone generator. Oxygen (02) introduced from the oxygen gas supply pipe 306 is converted into ozone (Ol), and the ozone introduction pipe 3
Sent to 04. 308 is a low pressure mercury lamp that irradiates ultraviolet light to promote the reaction.

このようなオゾン洗浄装置の反応炉301の中に、ヒー
タ303により200℃以下に加熱した試料102を置
き、濃度200g/Nmのオゾン(Ol)を導入するこ
とにより試料表面の不純物をオゾンとの反応により取除
くことができる。このとき、紫外光を照射することによ
り、試料102表面のオゾン(O5)との反応は促進さ
れ洗浄の効果は向上する。
A sample 102 heated to 200° C. or lower by a heater 303 is placed in the reactor 301 of such an ozone cleaning device, and ozone (Ol) with a concentration of 200 g/Nm is introduced to remove impurities on the sample surface. Can be removed by reaction. At this time, by irradiating ultraviolet light, the reaction with ozone (O5) on the surface of the sample 102 is promoted and the cleaning effect is improved.

第2図に示した半導体装置の製造方法において、第2図
(b)の洗浄工程を上述のオゾン洗浄装置を用いた洗浄
により行い、耐湿性を向上させた半導体装置の製造が可
能である。
In the method for manufacturing a semiconductor device shown in FIG. 2, the cleaning step shown in FIG. 2(b) can be performed by cleaning using the above-mentioned ozone cleaning device, thereby making it possible to manufacture a semiconductor device with improved moisture resistance.

第4図に、本発明により製造した半導体装置について耐
湿性実験を行った結果を示す。試料としては、(1)ポ
ンディング後に絶縁膜の被覆をせず樹脂封止した従来の
半導体装置、(2)ポンディング後に洗浄せず5in2
膜を被覆し樹脂封止した半導体装置、 (3)ポンディ
ング後にアルゴンスパッタエツチングによる洗浄を行い
、次いで絶縁膜(SiO2)を被覆し樹脂封止を行った
本発明の第1の実施例による半導体装置、(4)ポンデ
ィング後にオゾンによる洗浄を行い、次いで絶縁膜(S
iO□)を被覆し樹脂封止を行った本発明の第2の実施
例による半導体装置の4種類各々100個について調べ
た。
FIG. 4 shows the results of a moisture resistance experiment conducted on a semiconductor device manufactured according to the present invention. The samples include (1) a conventional semiconductor device sealed with resin without covering with an insulating film after bonding, and (2) a 5in2 semiconductor device without cleaning after bonding.
(3) A semiconductor device according to a first embodiment of the present invention in which a semiconductor device is coated with a film and sealed with a resin; (3) a semiconductor device is cleaned by argon sputter etching after bonding, and then covered with an insulating film (SiO2) and sealed with a resin; (4) Cleaning with ozone after bonding, then insulating film (S
100 pieces of each of four types of semiconductor devices according to the second embodiment of the present invention coated with iO□ and sealed with resin were examined.

耐湿性試験は、240℃のハンダに試料を浸漬した後、
150℃2気圧の水蒸気釜に試料を入り不良数を調べる
RCT (プレッシャー・クツカー・テスト)を行った
For the moisture resistance test, after immersing the sample in solder at 240°C,
An RCT (Pressure Kutzker Test) was conducted by placing the sample in a steam oven at 150°C and 2 atm pressure to determine the number of defects.

ポンディング後に絶縁膜(SiO2)被覆を行わない従
来の半導体装置に対して、ポンディング後に半導体素子
表面を洗浄し絶縁膜(SiO2)の被覆を行った本発明
による半導体装置が耐湿性において優れていることが示
される。
In contrast to conventional semiconductor devices that do not coat with an insulating film (SiO2) after bonding, the semiconductor device of the present invention, in which the surface of the semiconductor element is cleaned and coated with an insulating film (SiO2) after bonding, has excellent moisture resistance. It is shown that there is.

上記耐湿性試験は再現性を確認するために製造時期の異
なる半導体装置を用いて繰返し行われた。
The above moisture resistance test was repeated using semiconductor devices manufactured at different times to confirm reproducibility.

洗浄工程を行わずにポンディング後絶縁膜(SiO2)
の形成を行った半導体装置は耐湿性試験の結果にははっ
きりとした再現性がない(第4図の斜線範囲)。これに
対し、本発明による半導体装置の結果は再現性がよい。
Insulating film (SiO2) after bonding without cleaning process
There is no clear reproducibility in the moisture resistance test results of the semiconductor device in which the semiconductor device was formed (the shaded area in FIG. 4). In contrast, the results of the semiconductor device according to the present invention have good reproducibility.

この事実は、半導体装置の製造工程(拡散工程および組
立工程)において半導体素子表面に付着する不純物の量
がばらつきがあることを示している。そして、本発明に
よる洗浄工程でこれら不純物が除去できることを示して
いる。
This fact indicates that there are variations in the amount of impurities that adhere to the surface of the semiconductor element during the manufacturing process (diffusion process and assembly process) of the semiconductor device. This shows that these impurities can be removed by the cleaning process according to the present invention.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、半導体素子の電極パッド
と外部導出線とが金属導線で接続され、かつ少なくとも
電極パッド部分が絶縁膜により被覆された半導体装置の
製造において、前記絶縁膜による被覆工程前に半導体素
子表面を洗浄する工程を設けることによって、耐湿性の
向上した半導体装置を再現性よく実現することができる
As explained above, the present invention provides a method for manufacturing a semiconductor device in which an electrode pad of a semiconductor element and an external lead wire are connected by a metal conductive wire, and at least the electrode pad portion is covered with an insulating film. By providing a step of cleaning the surface of the semiconductor element beforehand, a semiconductor device with improved moisture resistance can be realized with good reproducibility.

また、上記実施例においては、本発明による洗浄工程を
ポンディング工程後に行ったが、これに限定されるもの
ではない。例えば、清浄な組立ラインにより組立工程を
行った場合、本発明による洗浄工程は絶縁膜による被覆
工程前であれば組立工程の任意の場所で行うことができ
る。
Further, in the above embodiments, the cleaning process according to the present invention was performed after the bonding process, but the invention is not limited to this. For example, when the assembly process is performed on a clean assembly line, the cleaning process according to the present invention can be performed at any location in the assembly process before the coating process with the insulating film.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例において用いられるアル
ゴンスパッタリング装置の断面図、第2図(a)〜(d
)は本発明の第1および第2の実施例の主な工程を説明
するための断面図、第3図は第2の実施例において用い
られるオゾン洗浄装置の断面図、第4図は本発明の効果
を示すための信頼性試験の結果を示す図である。 101・・・・・・反応炉、102・・・・・・試料、
103・・・・・下部電極、104・・・・・・ブロッ
キングコンデンサ105・・・・・・高周波電源、10
6・・・・・・上部電極、107・・・・・・アルゴン
ガス導入管、108・・・・・・真空排気管、201・
・・・・・リードフレーム(リード部)、202・・・
・・・リードフレーム(グイバット部)、203・・・
・・・半導体素子(チップ)、204・・・・・・電極
パッド、205・・・・・・保護膜、206・・・・・
・金線、207・・・・・・アルゴン放電又はオゾン、
208・・・・・・絶縁膜。
FIG. 1 is a cross-sectional view of an argon sputtering apparatus used in the first embodiment of the present invention, and FIGS. 2(a) to (d)
) is a cross-sectional view for explaining the main steps of the first and second embodiments of the present invention, FIG. 3 is a cross-sectional view of the ozone cleaning device used in the second embodiment, and FIG. 4 is a cross-sectional view of the ozone cleaning device used in the second embodiment. FIG. 3 is a diagram showing the results of a reliability test to show the effect of the method. 101... Reactor, 102... Sample,
103...Lower electrode, 104...Blocking capacitor 105...High frequency power supply, 10
6... Upper electrode, 107... Argon gas introduction pipe, 108... Vacuum exhaust pipe, 201...
...Lead frame (lead part), 202...
...Lead frame (guibat part), 203...
... Semiconductor element (chip), 204 ... Electrode pad, 205 ... Protective film, 206 ...
・Gold wire, 207... Argon discharge or ozone,
208...Insulating film.

Claims (3)

【特許請求の範囲】[Claims] (1)半導体素子の電極パッドと外部導出線とが金属導
線により接続され、少なくとも前記電極パッドが絶縁膜
により被覆された半導体装置の製造方法において、前記
絶縁膜による被覆工程前に少なくとも前記電極パッド表
面を洗浄する工程を有することを特徴とする半導体装置
の製造方法
(1) In a method for manufacturing a semiconductor device in which an electrode pad of a semiconductor element and an external lead wire are connected by a metal conductive wire, and at least the electrode pad is covered with an insulating film, at least the electrode pad is A method for manufacturing a semiconductor device, comprising a step of cleaning the surface.
(2)前記電極パッド表面の洗浄工程が不活性ガス放電
雰囲気中に前記電極パッド表面を晒すことによるスパッ
タエッチング工程である請求項1記載の半導体装置の製
造方法
(2) The method for manufacturing a semiconductor device according to claim 1, wherein the step of cleaning the surface of the electrode pad is a sputter etching step by exposing the surface of the electrode pad to an inert gas discharge atmosphere.
(3)前記電極パッド表面の洗浄工程が、オゾンガス雰
囲気中に前記半導体素子を放置する工程である請求項1
記載の半導体装置の製造方法
(3) Claim 1, wherein the step of cleaning the surface of the electrode pad is a step of leaving the semiconductor element in an ozone gas atmosphere.
Method for manufacturing the described semiconductor device
JP63261820A 1988-10-17 1988-10-17 Method for manufacturing semiconductor device Expired - Lifetime JP2674144B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63261820A JP2674144B2 (en) 1988-10-17 1988-10-17 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63261820A JP2674144B2 (en) 1988-10-17 1988-10-17 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH02106942A true JPH02106942A (en) 1990-04-19
JP2674144B2 JP2674144B2 (en) 1997-11-12

Family

ID=17367182

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63261820A Expired - Lifetime JP2674144B2 (en) 1988-10-17 1988-10-17 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2674144B2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5292478A (en) * 1976-01-30 1977-08-03 Hitachi Ltd Semiconductor device and its preparation
JPS56116633A (en) * 1980-02-20 1981-09-12 Hitachi Ltd Semiconductor device
JPS61101040A (en) * 1984-10-24 1986-05-19 Hitachi Ltd Bonding device
JPS63244660A (en) * 1987-03-30 1988-10-12 Hitachi Cable Ltd Assembling method for semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5292478A (en) * 1976-01-30 1977-08-03 Hitachi Ltd Semiconductor device and its preparation
JPS56116633A (en) * 1980-02-20 1981-09-12 Hitachi Ltd Semiconductor device
JPS61101040A (en) * 1984-10-24 1986-05-19 Hitachi Ltd Bonding device
JPS63244660A (en) * 1987-03-30 1988-10-12 Hitachi Cable Ltd Assembling method for semiconductor device

Also Published As

Publication number Publication date
JP2674144B2 (en) 1997-11-12

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