JPH02106943A - Mounting structure of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To inhibit a voltage drop by wiring resistance at a low value by conducting connection by a metallic lead bonded with a metallic protrusion through a thermocompression bonding method, etc., in the peripheral section of a VLSI chip and connection by a metallic protrusion formed at the central section of the VLSI chip. CONSTITUTION:There are two kinds of the connection of a peripheral section, in which metallic leads 4 bonded with metallic protrusions 2 shaped to the peripheral section of a VLSI chip through a thermocompression bonding method, etc., are cemented to metallic protrusions 6 formed onto a circuit board 7, and the connection of a central section, in which bumps 3 shaped at the central section of the VLSI chip 1 are connected to the metallic protrusions 6 of the circuit board 7 through solder 5, in the connection of the wirings of the VLSI chip 1 and the mounting wirings 9 of the circuit board 7. Both are jointed with the specified wirings of another VLSI chip 1 or predetermined external connecting pins 8 through the mounting wirings 9 of the surface of the circuit board 7 or internal mounting wirings 10.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to the implementation of semiconductor integrated circuits, and in particular to implementation useful for system hardware applications such as ultra-high-speed, cutting-edge supercomputers or large general-purpose computer computers that use bipolar devices. It concerns the structure and its manufacturing method.

[Conventional technology]

Conventionally, tape automated bonding (hereinafter referred to as TAB) method and flip chip method are known as this type of mounting method. The former method connects the leads of the carrier tape at the periphery of the chip by adhering them, and the latter method connects them inside the chip by soldering with solder bumps.

[Problem to be solved by the invention]

In order to satisfy system hardware needs, VLSI technology is required to further increase the integration and speed of LSI chips. VLSI chips are becoming larger and larger and are being packaged in different bins. This trend is expected to continue in the future.

Conventional mounting methods such as the above-mentioned TAB method and flip-chip method are unable to respond to future trends as described below.

First, since the TAB method provides connections with external leads only at the periphery of the VLSI chip, power must be supplied to the center of the large VLSI chip through the wiring of the VLSI chip.

Supplying power through such long wiring results in a large voltage drop due to wiring resistance. It is a bipolar VLSI chip (ECL) commonly used for high-speed applications.
This is an extremely serious problem for electronic devices (which have shaped circuits as their constituent elements). This is because the voltage drop caused by the wiring resistance changes the emitter-base (E-B) bias of the bipolar transistor, causing large variations in current. It is said that implementation using the TAB method, which is currently in practical use and is widely used, is facing a technological barrier in responding to future technological trends.

On the other hand, mounting using the flip-chip method has long been viewed as problematic from a practical standpoint, and the reality is that it is only used for extremely limited special purposes. The high level of technical hurdles that have prevented most manufacturers, except for a few, from putting it into practical use, will become a more serious problem when trying to cope with the larger size and multi-bin size of VLS I chips. is considered. That is, in flip-chip bonding, since the connection is made face-down to the circuit board, the pattern to be connected on both the VLSI chip side and the circuit board side cannot be visually seen, and sufficient alignment accuracy cannot be obtained. It is said that self-alignment is possible due to the surface tension of the solder if an appropriate flow is performed, but VLSI
In a state where the number of solder bumps increases, the bump pitch becomes narrower, and the area where the bumps are formed becomes larger, as with chips, it is not possible to perform the process as smoothly as expected on paper.

The flip-chip method for VLS I chips has not yet been put into practical use despite intensive development efforts, which clearly indicates the technical difficulties involved in mass production. I can say that it is. Furthermore, in order to maintain the reliability of the system hardware, VLSI chips must be thoroughly screened and burn-in tested to eliminate defects that can cause early failures, but the flip-chip method requires a large number of steps in this regard. Blobbing onto shaped bumps is actually extremely difficult and impossible.

[Means to solve the problem]

In the mounting structure of the present invention, when connecting the wiring of the VLSI chip and the mounting wiring of the circuit board, the connection is made using a metal lead attached to a metal protrusion at the periphery of the VLSI chip by thermocompression bonding, etc., and the connection is provided at the center of the VLSI chip. It has a connection using a metal protrusion (bump).

The bump connection provided in the center is used to supply power to the center of the VLSI chip and its vicinity, while the metal lead is used for signal purposes and to supply power to the periphery and its vicinity. . The wiring on the VLSI chip is designed so that burn-in testing during the manufacturing process can be performed without the need to provide electrical connections to the bumps in the center of the VLSI chip, that is, using only the metal leads around the periphery of the VLSI chip. . Incidentally, after the selection and inspection of VLSI chips, the bumps in the center are also blown to make electrical connection.

Further, it is also possible to extend the metal lead for power supply purpose formed on the periphery of the VLSI chip toward the center of the VLSI chip, and connect one or more leads to the wiring of the VLSI chip at the extended portion.

The bumps provided at the center of the VLSI chip can be provided at the same time as the metal protrusions provided at the periphery of the VLSI chip for bonding metal leads.

The above mounting structure consists of a process of forming metal protrusions on the periphery of the VLSI chip and a bump in the center, a process of bonding the metal leads of the tape carrier mounting to the metal protrusions on the periphery, and a measurement on the carrier tape connected to the metal leads. The process of inspecting and sorting VLSI chips by blowing (connecting a measurement probe) to the pads and bumps in the center, VL
A process of burn-in testing the SI chip to remove defects that cause early failures, a process of cutting the metal leads all at once and separating them from the carrier tape, a process of connecting the metal leads on the periphery of the VLSI chip to the mounting wiring of the circuit board, and It can be manufactured by a method that includes the step of connecting the central bump to the mounting wiring of the circuit board.

In this manufacturing method, when connecting the bumps at the center of the VLSI chip to the mounting wiring on the circuit board, alignment is performed using the metal leads at the periphery. This can be done by aligning your eyes with the pattern. These alignments are performed by visually (using a microscope) aligning predetermined metal leads on the periphery with predetermined wiring patterns on the circuit board.

〔Example〕

Hereinafter, the details of the present invention will be explained based on the drawings.

FIG. 1 is a plan view showing an embodiment of the present invention. Second
The figure is a sectional view taken along line AA' in FIG. 1. 1 and 2 illustrate the following points.

Roughly speaking, a VLSI chip is one in which 106 or more elements are formed per chip and whose size exceeds 10 mm. The VLSI chip 1 is mounted face down on a circuit board 7. Although only one VLSI chip 1 is shown in FIGS. 1 and 2, this is just a portion of the whole, and in reality, multiple chips are mounted on the circuit board 7. .

Wiring of VLSI chip 1 (not shown in the diagram) and circuit board 7
The connection with the mounting wiring 9 is a peripheral connection in which a metal lead 4 is bonded to a metal protrusion 2 provided on the periphery of the VLSI chip by thermocompression bonding or the like, and is bonded to a metal protrusion 6 provided on the circuit board 7. and a bump 3 provided in the center of the VLSI chip 1.
to the metal protrusion 6 of the circuit board 7 via the solder 5,
The central part has two types of connections. Both connections are made via mounting wiring 9 on the surface of the circuit board 70 or internal mounting wiring 10.
It is connected to a predetermined wiring of another VLSI chip 1 (not shown in the figure) or a predetermined external connection pin 8 via the VLSI chip 1 .

The specific contents of each part in this embodiment are as follows. The metal protrusions 2 and bumps 3 are formed simultaneously by electroplating and have a height of about 10 to 20 μm and a size of 80 μm.
The size is 80 μm and Au is used as the material. The metal protrusion 6 is also electroplated to a height of approximately 50 μm and a size of 100 μm.
The size is m×100 μm and Au is used as the material.

The metal lead 4 is made of Au, has a width of 100 μm, a thickness of 3 μm, and a length of 1 to 30.

The metal protrusion 2 and the metal lead 4 and the metal protrusion 6 and the metal lead 4 are each bonded by thermocompression bonding with a load applied at 400° C. or higher.

As the solder 5, Pb-8n solder is used. In this embodiment, the sPbSn solder is bonded to the metal protrusion 6 in advance, and the VLSI is bonded by bonding the metal lead 4.
After the chip 1 is fixed, a reducing atmosphere (e.g. H,
The central connection was made through a flow furnace with a peak temperature of about 350° C. filled with gas. In this example,
Even though no flux was used, sufficient soldering was achieved.

The circuit board 7 is a multilayer ceramic board with a size of about 100 mm, and the mounting wiring 9 and the IO1 external connection bin 8 are similar to those used conventionally.

FIGS. 3(a) to 3(a) are cross-sectional views showing an embodiment of the manufacturing method of the present invention. FIG. 3(a) shows metal protrusions 2 on the periphery of a VLSI chip 1 and bumps 3 on the central part. This shows that Au is electroplated onto a base metal such as Ti or Pt-Ti with the parts other than the parts corresponding to metal protrusions 2 and bumps 3 covered with a thick film resist with a film thickness of 20 μm. raised by the method, metal protrusion 2 and bump 3
was formed in this embodiment, but it goes without saying that it can be formed using other materials and other processes. Furthermore, instead of forming the metal protrusions 2 and bumps 3 at the same time as in this embodiment, they may be formed individually in a manner convenient for subsequent steps.
It is also possible to use different materials.

FIG. 3(b) shows a bonding tool 1 on a metal protrusion 2 of a metal lead VLSI chip 1 formed on a carrier tape 13 with a width of 35 mm to 70 mm or larger.
6 indicates that thermocompression bonding was performed while applying a load. Although not shown in the figure, a heater is embedded in the tip of the bonding tool 16, and is designed to heat the thermocompression bonding portion to about 400°C. In that state, several 10 kg/a
Heat compression bonding is performed by applying a load of nt. Sprocket holes 15 for running the tape are provided at both ends of the carrier tape 13. Furthermore, a measurement pad 14 is provided at the tip of each metal lead 4, which is eventually cut off and no longer used, but is used during the manufacturing process. In the figure, a portion surrounded by a broken line circle is a local perspective view for explaining the point.

FIG. 3(c) shows that the probe 17 is brought into contact with the above-mentioned measurement pad 14 and the bump probe 18 is brought into contact with the bump 3 for screening inspection. The VLSI chips are extracted to the outside through such electrical connections, and the VLSI chips are selected and inspected using a tester. This process is actually much easier than the flip-chip method.
You can enjoy the blobbing of method B. For this purpose, by using appropriate jigs and tools, although not shown in the diagram,
Burn-in tests such as high temperature bias application (BT) tests and operation tests are possible.

FIG. 3(d) shows that the VLSI chip 1 that passed the screening inspection and burn-in test was cut and separated from the carrier tape 13 by the punching/forming tool 19, and the metal leads 4 were formed as shown in the figure. .

The length of the metal lead 4 after cutting is about 1 to 3 lengths. The reason why the metal leads 4 are formed is as described below.
When the VLSI chip 1 is mounted face down on the
The main surface of the VLSI chip 1 should not come into contact with the mounting wiring on the surface of the circuit board 7, and the bump 3 in the center of the VLSI chip 1 should be
This is to create a space for making connections.

FIG. 3(e) shows the circuit board 7 at a predetermined position.
), the VLSI chip 1 described in section 1 is aligned, and the metal leads 4 are thermocompression bonded to the metal protrusions 6 on the circuit board 7 using the bonding tool 20. VLSI chip 9
For alignment, ■ Back side of LSI chip 1 (upper side of figure)
This is done by visually aligning a predetermined metal lead 4 and a predetermined metal protrusion 6. By such positioning, the bumps 3 and the metal protrusions 6 can be aligned automatically and with high precision. In principle, the deformation of the metal leads 4 will reduce the accuracy of alignment, but this alignment method is much more accurate than the alignment method used in the flip-chip method, which aligns the corner of the chip with the pattern on the circuit board. good. - To give an example, while the conventional alignment method had an accuracy of about ±10 μm, this alignment method can achieve an accuracy of ±5 μm or less.

For connection at the center, a solder 5 whose composition is Pb and Sn is placed between the bump 3 and the metal protrusion 6. In the case of this example, the metal lead 4 was bonded by thermocompression using the bonding tool 20 with the solder 5 bonded to the metal protrusion 6 in advance. Note that the method of arranging the solder 5 between the bump 3 and the metal protrusion 6 is not limited to the above-mentioned embodiment; for example, by adding electroplating to the bump 3 side,
Build up Pb and Sn (at this time, cover the metal protrusions 2 with a thick film resist to prevent them from rising)
But it is possible. Furthermore, the material of the solder 5 does not have to be limited to the Pb-Sn composition of this embodiment, and the metal protrusion 3 and the metal protrusion 6 are melted at a temperature that does not destroy the adhesion of the metal lead 4, that is, about 400°C or less. Any material that can be bonded can be used.

FIG. 3 (") shows that the metal protrusion 3 and the metal protrusion 6 are melted and bonded with the solder 5 through a flow furnace. In this embodiment, the reflow furnace contains reducing H
2 gas, and good adhesion can be obtained without using special flux for soldering. Of course, soldering is possible here using flux.

The peak temperature of the reflow oven in this example is approximately 350°C
The metal leads 4, while bonded to the metal protrusions 2 and G, pass through a TV reflow oven to fix the VLSI chip 1 in a predetermined position during the soldering described above. Therefore, the defective chip position shift during soldering, which has often occurred in the conventional flip-chip method, is prevented.

The metal protrusion 3 and the metal protrusion 6 are mechanically firmly connected by the solder 5, so that the VLSI chip 1 and the circuit board 7
Thermal stress occurs due to a mismatch in the coefficient of thermal expansion between the two. However, the connection is formed only in a narrow area at the center of the VLSI chip 1, and therefore, the maximum thermal stress generated is small, and sufficient resistance to temperature cycle tests can be obtained. This is one of the advantages of the present invention, which is similar but essentially different from the flip-chip method in which all connections, including signal connections, are mechanically fixed connections. It is.

FIG. 4 is a sectional view showing another embodiment of the present invention. The numbers of the parts shown in the figure that are the same as those in FIG. 2 described above have the same contents. Omitted to avoid duplication of explanation.

In FIG. 4, what is particularly provided in this embodiment is V.
One or more metal protrusions 11 are provided between the metal protrusions 2 provided on the periphery of the LSI chip 1 and the bumps 3 provided in the center. Among the metal leads 4, those for power supply are extended into the inside of the VLSI chip 1 and bonded to metal protrusions 11. By adding the power supply using the metal protrusion 11, the power supply wiring on the vLSI chip becomes shorter, and the voltage drop is reduced accordingly. When adopting a circuit design that is more sensitive to voltage drops, or
When the LSI chip 1 is further enlarged, this structure becomes
Extremely useful.

Although not shown in the diagram, connecting the metal protrusion 11 to the metal protrusion 2 or bump 3, or both at the same potential, using wiring on the chip may also reduce the voltage drop in the case of a chip layout with short wiring lengths. Some effect can be obtained in reducing the

It is also desirable to reduce the resistance of the mounting wiring on the circuit board 7 side connecting the VLSI chip 1 and the external connection pins 8 as much as possible. For that purpose, the VLS
A greater effect can be obtained by connecting the power supply system with mounting wiring that connects the I-chip mounting surface side and the external connection pin 8 formation surface side.

〔Effect of the invention〕

As explained above, the present invention provides power supply connections not only at the periphery of the VLSI chip, but also at the center, or in some cases, at an intermediate location between the periphery and the center.
Bipolar ECL is extremely useful for high-speed applications as it is possible to keep the voltage drop due to wiring resistance low even when the I-chip becomes larger, unlike the conventional TAB mounting method.
This has the effect of allowing system circuits to be used. By moving the power supply connections internally, the metal leads on the periphery can be used for signal purposes, effectively increasing the number of bins.

Furthermore, since sufficient selection inspection and burn-in testing can be performed during the manufacturing process, highly reliable system hardware can be obtained. For this reason, the cost of testing the system hardware is significantly reduced, and the total cost can be lowered compared to mounting using the flip-chip method.

Furthermore, when connecting the bumps in the center of the VLSI chip to the mounting wiring on the circuit board, the metal leads on the periphery can be used to visually align the bumps, making it possible to perform high-precision alignment, and the pitch between the bumps. This has the effect of making it possible to narrow the number of bins, thereby increasing the number of bins.

[Brief explanation of drawings]

Fig. 1 is a plan view showing the mounting structure of the present invention, and Fig. 2 is a plan view showing the mounting structure of the present invention.
3(a) to 3(a) are sectional views showing the manufacturing method of the present invention, and FIG. 4 is a sectional view showing another mounting structure of the present invention.1 ... VLSI chip, 2 ... Metal protrusion, 3 ... Bump, 4 ... Metal lead, 5 ... Solder 6 ... ...metal protrusion,
7... Circuit board, 8... External connection bin, 9... Mounted wiring (surface), 10...
Mounting wiring (internal), 11...Metal protrusion, 12.
... Mounting wiring, 13 ... Carrier tape, 14 ... Measuring pad, 15 ... Sprocket hole, 16 ... Ponding tool, 17. Old probe, 8. Bump probe, 9. Punching & forming tool, 20. Ponding tool.

Claims (1)

[Claims] In a semiconductor integrated circuit mounting structure in which a plurality of semiconductor integrated circuit chips are mounted on a circuit board equipped with mounting wiring, when connecting the wiring of the semiconductor integrated circuit chip and the mounting wiring of the circuit board, it is necessary to A mounting structure for a semiconductor integrated circuit characterized in that the connection is made not only by metal leads formed on the periphery but also by a metal protrusion provided in the center of the semiconductor integrated circuit chip.