JPH02106963A - Complementary type mos integrated circuit - Google Patents

Abstract

PURPOSE:To interrupt a harmful current path even when the power supply of either one circuit of both circuits is brought to an OFF state when outputs from two integrated circuits are connected to a common bus, and to use the title integrated circuits safely by installing an N-MOST as a switch between a P-MOST and an N-MOST constituting an output circuit. CONSTITUTION:An N-MOST 31 is added, and its source is connected to the drain of a P-MOST 1, its drain to the source of an N-MOST 2 and its gate to a power terminal 3 together with the source of the P-MOST 1 and a bulk. The N-MOST 2 is brought to an ON state when input voltage A and B is brought to 'H' at the time of normal operation (when a power supply is brought to the ON state) when an 'H' or 'L' output is emitted to an output terminal X, and 'L' is output to the output terminal X. When input voltage A and B is brought to 'L', the P-MOST 1 and the N-MOST 31 are brought to the ON state, and voltage acquired by substracting a voltage drop between the source- drain of the P-MOST 1 and a voltage drop between the source-drain of the N-MOST 31 from VCC is output as 'H' to the output terminal X.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit using complementary MO8 (hereinafter referred to as CMO8) transistors, and particularly relates to an improvement in the output section thereof.

[Conventional technology]

FIG. 4 is a circuit diagram showing a conventional output circuit composed of CMOS transistors, (1) is a P-channel MOS transistor (hereinafter referred to as P-MOST), and (2) is a P-channel MOS transistor (hereinafter referred to as P-MOST).
MO8T (1) is an n-channel MOS transistor (hereinafter referred to as n-MOST) connected in series so that its drain is commonly connected, and (3) is a P-MOST (1).
) to supply the voltage VCC to the source of the original terminal, (4) is the GND terminal that grounds the source of n-MO8T (2),
(G) is an input terminal that provides input A to the gate of P-MO3T (1), (B) is an input terminal that provides input B to the gate of n-MO8T (2), and (3) is an input terminal that provides input A to the gate of P-MOST (1). ) and n-MOST (2). This circuit has output
This is a tri-state circuit having three states: (2) are both off states).

FIG. 5 is a block diagram showing an application example in which two integrated circuits including the output circuit shown in FIG. 4 are connected to a common bus. In the figure, 01 is the first integrated circuit, and the power terminal (
3) is supplied with the voltage VCCI, the ground terminal (4) is grounded, and outputs X. (1) is the second integrated circuit, N
The voltage VCC2 is supplied to the source terminal (to), and the ground terminal α
→ is grounded, outputs Y, and 1° (7) is a common bus. In the configuration shown in Fig. 5, the output X is connected to the common bus (1)
When sending the output Y to the common bus ■, the second integrated circuit (A) is controlled to make the output terminal (G) high impedance, and when the output Y is sent to the common bus ■, the first integrated circuit C1O is controlled to make the output terminal (G) high impedance. By making (3) high impedance, there is no mutual interference and the bus (7) can be shared.

FIG. 6 is a detailed diagram of the output section of the circuit shown in FIG.
ST(2), the bulk of each is connected to the source, and the source-drain connection is as explained in FIG. In the figure, (8) and (9) are gate terminals of P-MOST (1) and n-MOST (2), respectively. Further, the output section of the second integrated circuit (A) is composed of P-MOSTQl) and n-MOSTQl,
In the figure, (to) and (1'J) are respectively similar gate terminals, and their configurations are exactly the same as the corresponding parts of the first integrated circuit a0.In addition, the output terminal (3) and the power supply terminal (3) Parasitic diodes (and) are formed between the output terminal (to) and the ground terminal (4), and parasitic diodes (and) are formed between the output terminal (to) and the power supply terminal (to) and the ground terminal (α4), respectively. It is formed.

In Fig. 6, when sending the output X to the common path line, the gate terminal (to) is set to "H", and the gate terminal
1 to L'' to make the output terminal (G) high impedance. On the other hand, when sending out the output Y, the gate terminal (
8) to "H" and gate terminal (9) to "IIL",
The output terminal (X) is set to high impedance.

[Problem to be solved by the invention]

Conventional integrated circuits were configured as follows, so when either the first or second integrated circuit is powered off, the output of the integrated circuit to which the power supply voltage is applied is H'', when the output of the integrated circuit on the off-state side is high impedance, the parasitic diode and P-MO
There is a problem in that current flows between the two power supply terminals through the ST, which adversely affects the circuit system and may even lead to destruction.

That is, when voltage VCC2 is off, output X = IIH
When I + output Y = high impedance, power supply terminal (3) →
Source-1 drain of P-MO8T (1) → Output terminal X
A current flows through the path =Y→parasitic diode □→power terminal a3. In addition, the pressure on the gate terminal (to) of P-MO8TQυ and the gate terminal Ql of n-MOST (6) is the voltage V
Since CC2 is turned off, it becomes unstable and the P-MOS
T (on state of lυ occurs, power supply terminal (a) -> P
-MOST tl) source → drain → output terminal x
=Y-+P-MO8T Ql) Current also flows through the drain-source → power supply terminal @ path.

This invention was made to solve the above-mentioned problems, and its purpose is to obtain a CMO8 integrated circuit that can share an output bus even when one of the power supplies is off. .

[Means for Solving the Problems] A CMO3 integrated circuit according to the present invention has an n-MOST as a switching element inserted between a P-MOST and an n-MOST that constitute an output circuit.

[Effect]

In this invention, in which the respective outputs of two CMOS integrated circuits are supplied to a common output bus, one of the CMOS integrated circuits is powered off to make the output high impedance, and one of the remaining Even if the output of the CMOS integrated circuit is IeH, the CMOS integrated circuit
Regarding the MOS integrated circuit, when the n-MOS T as a switching element inserted in the output circuit is turned off, the current path formed via the P-MOST and the parasitic diode that constitutes the output circuit is cut off. .

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and the same reference numerals as in the conventional circuit designate the same parts, so the explanation thereof will be omitted. FIG. 1 is used when the ground voltages of the two circuit systems are the same and one of the power supplies is in an off state.

The essential logical configuration is the same as the conventional one shown in Figure 4, but
The difference is that N-MOSTc]I) is added, and N-M
OST C11) (7) Source is P MOST (
1), the drain of N-MOSTOυ is connected to the source of N-MOST (23, and N-Ni
08T c>D O') gate is connected to the power supply terminal (3) together with the P-MO8'ro) no source and bulk.

Fig. 2 is a circuit diagram that takes into account the parasitic diode of the embodiment shown in Fig. 1. When the N-MOSTOI) is in the off state, there is no current path from the output terminal (3) to the power supply terminal (3), and only one Even if the outputs of the two CMOS integrated circuits in which the power of the circuit (1) or (2) is turned off are connected to a common bus, there is no adverse effect on the circuit system as in the conventional case.

Consider a normal operation (when the power is on) in which a normal II H11 or II L II output is output to the output terminal (3).

When the input voltages A and B are 'H', L'' is output to n-MO3T (2j is in the on state and the output terminal is bad). That is, the same operation as the conventional one shown in FIG. 4 is shown.

Next, when input voltages A and B are +(L”, l)-M 0
5T(1) and n-MOSTC3]) are in the on state, and the voltage drop between the source and drain of P-MO3T(1) VSDP and the voltage drop between the source and drain of n-MO3TC(]) V5DN from VCC. Reduced voltage (V
cc Vsrip V5 opi) is the output terminal (
(G) is output as l(H+1). That is, the same operation as the conventional one shown in FIG. 4 is shown.

FIG. 3 is a cross-sectional view of the structure of the CMO3 integrated circuit shown in FIG.
-MO3T(3]) is 1MOST that constitutes the output circuit
Since it is formed in the same process as (2), n-IV40ST
There is no need to add a special process to form 6υ.

〔Effect of the invention〕

As described above, according to the present invention, P
- Since n-MO8T is installed as a switch between MOST and n-MOST, when connecting the outputs of two integrated circuits to a common bus, it can be used as a switch for the circuit whose output is high impedance. By turning off the n-MOST of both circuits, @
Even when the power source is turned off, harmful current paths are blocked and the device can be used safely, expanding the range of applications for CMOS integrated circuits.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram taking into account the parasitic diode of the output section of this embodiment,
Figure 3 is a cross-sectional view of the structure of the CMOS integrated circuit in Figure 1;
The figure is a circuit diagram showing the output section of a conventional CMOS integrated circuit, FIG. 5 is a block diagram showing an application example of the circuit in FIG. 4, and FIG. 6 is a detailed circuit diagram of the output section of the circuit in FIG. . In the figure, +1) is a P-channel MOS transistor, (2) is an n-channel MOS transistor, (3) is the second power supply terminal, (4) is the second power supply terminal (ground terminal), and C31) is the switch. n-channel MO as a device
S ) - transistor. In addition, the same symbols in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] A P-channel MOS transistor and a first n-channel MOS transistor are connected in series between a first power source and a second power source such that the P-channel MOS transistor is on the first power source side. In the connected output circuit, the P channel MOS transistor and the first n channel MOS
A second n-channel MOS transistor as a switching element is inserted between the transistor and the second n-channel MOS transistor, the source of the second n-channel MOS transistor being the drain of the P-channel MOS transistor, and the drain being the first n-channel MOS transistor. A P-type well region is formed in the n-type semiconductor substrate, and an output circuit is configured in the P-type well region. 1. A complementary MOS integrated circuit comprising a first n-channel MOS transistor and a second n-channel MOS transistor as a switch element.