JPH02107018A - Voltage controlled oscillator - Google Patents

Voltage controlled oscillator

Info

Publication number
JPH02107018A
JPH02107018A JP63259476A JP25947688A JPH02107018A JP H02107018 A JPH02107018 A JP H02107018A JP 63259476 A JP63259476 A JP 63259476A JP 25947688 A JP25947688 A JP 25947688A JP H02107018 A JPH02107018 A JP H02107018A
Authority
JP
Japan
Prior art keywords
stage
controlled oscillator
circuit
inverter
voltage controlled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63259476A
Other languages
Japanese (ja)
Inventor
Takashi Mori
茂利　隆司
Yoshinori Nagoya
名古屋　喜則
Toshiyuki Tsuchiya
土屋　敏之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
NTT Inc
Original Assignee
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Nippon Telegraph and Telephone Corp filed Critical Hitachi Ltd
Priority to JP63259476A priority Critical patent/JPH02107018A/en
Publication of JPH02107018A publication Critical patent/JPH02107018A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To limit the upper bound of oscillating frequencies by providing a limitter circuit, and limiting a current flowing through a control circuit. CONSTITUTION:Inverters 1 and 2 are cascaded by odd-number stages, the input of the initial stage inverter 1 is connected to the output terminal of the last stage inverter, and thus an annular oscillator is composed. Currents flowing through the respective stage inverters 1 and 2 are controlled by the input voltages of voltage controlled oscillator(VCO) control circuits 3 and 4, namely control terminal voltages, and the oscillating frequencies are changed. Further, since the currents flowing through the VCO control circuits 3 and 4 are limited by limitter circuits 5 and 6 on the lower stage of the VCO control circuits 3 and 4, the oscillating frequencies >= the specific frequencies are limited. In such a way, since the upper boundary of the oscillating frequencies can be limited, the non-operation or malfunction of a logical circuit on the next stage, etc., can be prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はＰＬＬに使用する高い発振周波数（数１００Ｍ
Ｈｚ）の電圧制御発振器（ＶＣＯ）に係夛、特に次段の
論理回路の動作速度に発振周波数を制限するに好適な電
圧制御発振器に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is applicable to high oscillation frequencies (several 100M) used in PLL.
The present invention relates to a voltage controlled oscillator (VCO), particularly suitable for limiting the oscillation frequency to the operating speed of the next stage logic circuit.

〔従来の技術〕[Conventional technology]

従来の電圧制御発振器は、特開昭５６−８６５０９号公
報に記載のように、奇数段のインバータを継続接続し、
上記インバータの初段の入力と最後段インバータの出力
端子とを接続し、上記インバータの各段に流入する電源
電流を制御電圧により制御する構成である。A conventional voltage controlled oscillator, as described in Japanese Unexamined Patent Publication No. 56-86509, continuously connects an odd number of stages of inverters.
The input of the first stage of the inverter is connected to the output terminal of the last stage inverter, and the power supply current flowing into each stage of the inverter is controlled by a control voltage.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記従来技術によるＶＣＯを用いてＰＬＬを構成する場
合には、ＶＣＯの発振周波数が次段の回路（分局器など
）が動作しないような高い周波数帯に入夛込むと、ＰＬ
Ｌの基本的な特性上から発振周波数をさらに上昇させる
ように動作しく実際には必要な発振周波数に対して十分
に高い周波数であるが、次段の回路が動作しないためあ
たかも発振周波数が極端に低い場合と同じような状態に
陥いる）、このためＰＬＬとしては目標以上の高い周波
数で発振したままとなって、希望する周波数に引き込め
なくなるという問題があった。When configuring a PLL using the VCO according to the prior art described above, if the oscillation frequency of the VCO enters a high frequency band where the next stage circuit (such as a branch divider) does not operate, the PLL
Due to the basic characteristics of L, it operates to further increase the oscillation frequency, and in reality it is a sufficiently high frequency for the required oscillation frequency, but since the next stage circuit does not operate, it appears as if the oscillation frequency is extremely high. Therefore, the PLL continues to oscillate at a frequency higher than the target, and cannot be pulled into the desired frequency.

本発明の目的は必要な高い周波数程度に発振周波数の上
限を制限できる電圧制御発振器を提供するにある。An object of the present invention is to provide a voltage controlled oscillator that can limit the upper limit of the oscillation frequency to a necessary high frequency.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的は、奇数段のインバータを縦続接続し、上記イ
ンバータの初段の入力と最後段インバータの出力端子と
を接続し、上記インバータの各段に流れる’を訛を制御
ｍ圧によ多制御する制御回路を備えた電圧制御発振器に
おいて、上記制御回路と電源（またはグランド）との間
にリミッタ回路を挿入し、上記制御回路に流れる電流を
制限するように構成した電圧制御発振器により達成され
る。The above purpose is to cascade inverters in an odd number of stages, connect the input of the first stage of the inverters to the output terminal of the last stage inverter, and control the flow rate of the inverters flowing to each stage of the inverters by m pressure. This is achieved by a voltage controlled oscillator equipped with a control circuit in which a limiter circuit is inserted between the control circuit and the power supply (or ground) to limit the current flowing to the control circuit.

〔作用〕[Effect]

上記電圧制御発振器は上記制御回路の入力電圧（制御電
圧）によりインバータの各段に流れる電流を制御するこ
とにより発振周波数を変化させることが可能であるが、
さらに上記リミッタ回路により上記制御回路に流れる電
流を制限することにより発振周波数の上限を制限するこ
とが可能となる。The voltage controlled oscillator can change the oscillation frequency by controlling the current flowing through each stage of the inverter using the input voltage (control voltage) of the control circuit.
Further, by limiting the current flowing through the control circuit using the limiter circuit, it is possible to limit the upper limit of the oscillation frequency.

〔実施例〕〔Example〕

以下に本発明の一実施例を第１図および第２図により説
明する。An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

第１囚は本発明による電圧制御発振器の一実施例を示す
ブロック図である。第１図において、１゜２はインバー
タ、３．４はＶＣＯ制御回路、５゜６はリミッタ回路、
７．８は抵抗器である。第１図のインバータ１．２は奇
数段に縦続接続し、初段インバータ１の入力と最後段イ
ンバータの出力端子とを接続して、リング状の発振器を
構成する。The first diagram is a block diagram showing an embodiment of a voltage controlled oscillator according to the present invention. In Figure 1, 1゜2 is an inverter, 3.4 is a VCO control circuit, 5゜6 is a limiter circuit,
7.8 is a resistor. The inverters 1.2 in FIG. 1 are connected in cascade in an odd number of stages, and the input of the first stage inverter 1 and the output terminal of the last stage inverter are connected to form a ring-shaped oscillator.

各段インバータ１．２に流れる電流はｖＣＯ制御回路３
．４の入力電圧すなわち制御端子電圧によ！り　！ｆＪ
御され、これによ）発振周波数を変化させることが可能
である。さらにｖＣＯ制御回路３．４に流れる電流はＶ
ＣＯ制御回路５．４の下段のリミッタ回路５．６により
制限され、これにより特定の周波数以上の発振周波数を
制限することが可能となる。この制限周波数はリミッタ
回路５．６の１を流を設定する抵抗器７．８の抵抗値Ｒ
１、Ｒ２を適洛に選ぶことにより自由に設定可能となる
。The current flowing through each stage inverter 1.2 is the vCO control circuit 3.
．． According to the input voltage of 4, that is, the control terminal voltage! the law of nature ! fJ
(by which the oscillation frequency can be changed). Furthermore, the current flowing through the vCO control circuit 3.4 is V
It is limited by the limiter circuit 5.6 at the lower stage of the CO control circuit 5.4, thereby making it possible to limit the oscillation frequency above a specific frequency. This limit frequency is determined by the resistance value R of resistor 7.8 which sets the limiter circuit 5.6.
1. By selecting R2 appropriately, it can be set freely.

第２図は本発明による電圧制御発振器の一実施例を示す
回路図である。第２図において、９〜１１はＰ−ＭＯ８
）ランジスタ、１２〜１９はＮ−ＭＯＳトランジスタ、
２０．２１は抵抗器である。第２図の奇数段の各インバ
ータはそれぞれＰ−ＭＯ８）ランジスタ？とＮ−ＭＯ８
）ランジスタ１２、Ｐ−ＭＯ８）ランジスタ１０とＮ−
ＭＯ８トランジスタ１５、Ｐ−ＭＯ８）ランジスタ１１
とＮ−ＭＯＳ　トランジスタ１４で構成され、リング状
の発振器を構成する。またＶ　ＣＯｆｌｔｌＪ御回路は
Ｎ−ＭＯＳトランジスタ１５，１６．１７で構成され、
該Ｎ−ＭＯＳトランジスタ１５，１６．１７のゲート電
圧すなわち制御端子電圧を変化させることにより、各イ
ンバータの電流が変えられるため発振周波数を制御する
ことが可能となる。さらに下段のリミッタ回路はＮ−Ｍ
ＯＳトランジスタ１８．１９で構成され、＃Ｎ−ＭＯＳ
トランジスタ１８．　１９の電流を固定すなわちゲート
電圧を固定することにより、特定の周波数以上の発振周
波数を制限することが可能となる。FIG. 2 is a circuit diagram showing an embodiment of a voltage controlled oscillator according to the present invention. In Figure 2, 9 to 11 are P-MO8
) transistors, 12 to 19 are N-MOS transistors,
20.21 is a resistor. Each odd-numbered stage inverter in Figure 2 is a P-MO8) transistor? and N-MO8
) transistor 12, P-MO8) transistor 10 and N-
MO8 transistor 15, P-MO8) transistor 11
and an N-MOS transistor 14, forming a ring-shaped oscillator. Further, the V COfltlJ control circuit is composed of N-MOS transistors 15, 16, and 17,
By changing the gate voltage, that is, the control terminal voltage, of the N-MOS transistors 15, 16, and 17, the current of each inverter can be changed, making it possible to control the oscillation frequency. Furthermore, the lower limiter circuit is N-M
Consists of OS transistors 18 and 19, #N-MOS
Transistor 18. By fixing the current of 19, that is, fixing the gate voltage, it becomes possible to limit the oscillation frequency above a specific frequency.

この発振周波数の上限は上記Ｎ−ＭＯ８）ランジスタ１
８．１９の電流すなわちゲート１圧を設定する抵抗器２
０．２１の抵抗値Ｒ５，Ｒ４を適当に選ぶことによ多自
由に設定可能となる。The upper limit of this oscillation frequency is the N-MO8) transistor 1 above.
8. Resistor 2 to set the current of 19 or gate 1 voltage
By appropriately selecting the resistance values R5 and R4 of 0.21, the resistance values can be freely set.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、電圧制御発振器（ＶＣＯ）の発振周波
数の上限を制限できるので、次段の論理回路などが不動
作あるいは誤動作することがなくな夛、高い発振周波数
（数１００ＭＩ（ｚ　）でＰＩ、Ｌに使用可能となる効
果がある、According to the present invention, it is possible to limit the upper limit of the oscillation frequency of a voltage controlled oscillator (VCO), thereby preventing the next stage logic circuit from malfunctioning or malfunctioning, and increasing the oscillation frequency to a high oscillation frequency (several 100 MI(z)). It has the effect of making it usable for PI and L.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明による電圧制御発振器の一実施例を示す
ブロック図、第２図は本発明による電圧制御発振器の一
実施例を示す回路図である。 １．２・・・インバータ、５．４・・・ＶＣＯ制向回向
回路。 ６・・・リミッタ回路、７．８・・・抵抗器、９〜１１
　　・・・ｐ−ＭＯＳトランジスタ、１２〜１９　・・
・Ｎ−ＭＯＳトランジスタ、２０〜２１　・・・抵抗器
。 代理人弁理士　小　川　勝　男ｆ２、FIG. 1 is a block diagram showing an embodiment of a voltage controlled oscillator according to the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the voltage controlled oscillator according to the present invention. 1.2... Inverter, 5.4... VCO control diversion circuit. 6...Limiter circuit, 7.8...Resistor, 9-11
...p-MOS transistor, 12-19...
・N-MOS transistor, 20-21...Resistor. Representative patent attorney Katsuo Ogawa f2,

Claims (1)

【特許請求の範囲】[Claims] １、奇数段のインバータを縦続接続し、上記インバータ
の初段の入力と最後段インバータの出力端子とを接続し
、上記インバータの各段に流入する電流を制御電圧によ
り制御する構成の電圧制御発振器において、発振周波数
の上限を制限するリミツタ回路を設けたことを特徴とす
る電圧制御発振器。1. In a voltage controlled oscillator having a configuration in which an odd number of stages of inverters are connected in cascade, the input of the first stage of the inverter is connected to the output terminal of the last stage inverter, and the current flowing into each stage of the inverter is controlled by a control voltage. , a voltage controlled oscillator characterized by being provided with a limiter circuit that limits the upper limit of the oscillation frequency.
JP63259476A 1988-10-17 1988-10-17 Voltage controlled oscillator Pending JPH02107018A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63259476A JPH02107018A (en) 1988-10-17 1988-10-17 Voltage controlled oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63259476A JPH02107018A (en) 1988-10-17 1988-10-17 Voltage controlled oscillator

Publications (1)

Publication Number Publication Date
JPH02107018A true JPH02107018A (en) 1990-04-19

Family

ID=17334608

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63259476A Pending JPH02107018A (en) 1988-10-17 1988-10-17 Voltage controlled oscillator

Country Status (1)

Country Link
JP (1) JPH02107018A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5686509A (en) * 1979-12-17 1981-07-14 Seiko Epson Corp Voltage controlled oscillator
JPS6290053A (en) * 1985-10-15 1987-04-24 Hitachi Cable Ltd Synchronization restriction method in phase-locked loop
JPS62290214A (en) * 1986-06-09 1987-12-17 Mitsubishi Electric Corp Phase locked oscillator
JPS6462023A (en) * 1987-09-02 1989-03-08 Hitachi Ltd Clock system for semiconductor integrated circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5686509A (en) * 1979-12-17 1981-07-14 Seiko Epson Corp Voltage controlled oscillator
JPS6290053A (en) * 1985-10-15 1987-04-24 Hitachi Cable Ltd Synchronization restriction method in phase-locked loop
JPS62290214A (en) * 1986-06-09 1987-12-17 Mitsubishi Electric Corp Phase locked oscillator
JPS6462023A (en) * 1987-09-02 1989-03-08 Hitachi Ltd Clock system for semiconductor integrated circuit

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