JPH02108111A - Stop detecting circuit for clock signal - Google Patents

Abstract

PURPOSE:To prevent the runaway of operation and breakage by obtaining a clock stop signal of invariably constant level without reference to whether a clock signal from the output terminal of an OR circuit stops at low or high level. CONSTITUTION:Once CS1 of the clock signal is applied to one input terminal of the OR circuit 2 to which a one-end grounded capacitor C1 and a resistance R1 applied with a specific voltage +5V through a 1st open collector NOT circuit 1 and the other CS2 of the clock signal CS is applied to the other input terminal of the OR circuit 2 to which a one-end grounded capacitor C2 and a resistance R2 applied with a specific voltage +5V are connected through a 2nd open collector NOT circuit 4. Therefore, the clock stop signal of invariably constant level is obtained without reference to whether the clock signal from the output terminal of the OR circuit 2 stops at the low or high level. Consequently, the runaway of operation and breakage are prevented.

Description

[Detailed Description of the Invention] (Required II) Regarding a clock signal stop detection circuit that plays an extremely important role in digital control circuits, etc., this invention detects the stop of a clock signal and operates the digital control circuit etc. based on the stoppage of the clock signal. By resetting the
In order to prevent the operation from running out of control or breaking down, one of the clock signals is connected to the first open collector NOT.
A circuit is formed in which a capacitor whose one end is grounded and a resistor to which a predetermined voltage is applied are connected through a circuit so that the clock signal is applied to one input terminal of an OR circuit, and the other end of the clock signal is applied to a NOT circuit. A circuit is formed such that the voltage is applied to the other input terminal of an OR circuit, which connects a capacitor with one end grounded and a resistor to which a predetermined voltage is applied, through a second open collector NOT circuit. The configuration is such that a clock stop signal of a constant level is always obtained from the output terminal of the OR circuit, regardless of whether the clock signal stops at a low level or a high level.

[Industrial application field]

The present invention relates to a stop detection circuit for a clock signal that plays an important role in various digital control circuits, such as a clock signal that forms the minimum unit in which a CPU processes a program in a computer.

[Conventional technology]

In various digital control circuits, such as computers, clock signals play an extremely important function, similar to the heart in animals.

Conventionally, there has been no device that detects the stoppage of this clock signal and resets the operation of a digital control circuit or the like based on the detection.

[Problem to be solved by the invention]

Therefore, if this clock signal stops, the operation of the digital control circuit etc. will run out of control or be damaged. Therefore, there is a problem in that it is necessary to quickly detect the stoppage of this clock signal and reset the operation of each control circuit including the CPU, for example.

An object of the present invention is to detect the stoppage of a clock signal and reset the operation of a digital control circuit based on the detection, thereby preventing the operation of the digital control circuit from running out of control or being damaged.

[Failure to solve the problem]

Means for solving the above problems in this invention will be explained with reference to the drawings.One side C81 of the clock signal C3 is connected to the capacitor C1 whose one end is grounded via the first open collector NOT circuit 1. and the specified voltage +
A circuit is formed such that it is applied to one input terminal of an OR circuit 2 connected to a resistor R, to which 5V is applied, and the other CS of the clock signal C3 is NOT times A? 83 and the second open collector NOT circuit 4, so as to be applied to the other input terminal of the OR circuit 2, which connects a capacitor C2 whose one end is grounded and a resistor R2 to which a predetermined voltage +5V is applied. A clock signal stop detection circuit configured to always obtain a clock stop signal of a constant level from the output terminal of the OR circuit 2, in which a clock signal is stopped at a low level or a high level. That is.

[Effect]

The clock signal is, for example, +5v and OV alternating in a short period of time with a very precise pulse width;
Since it is conceivable that the clock may stop at either y or Ov, it is necessary to obtain a clock stop signal no matter which state the clock stops at.

By the means described above, when the clock signal stops at Ov, the first open collector NOT circuit 1
The output from is at a high level (hereinafter referred to as 1''), that is, this first open collector NOT circuit l is in an open state, and the capacitor C1 is connected to +5V through the resistor R.
is charged, and one input terminal of the OR circuit 2 becomes "1".

On the other hand, since the output side of the NOT circuit 3 becomes "1",
The input side of the second open collector NOT circuit 4 is “
1”, the output side is low level (hereinafter referred to as “O”),
In other words, the second open collector NOT circuit 4 is in a closed circuit state, and the current passing through the resistor Rz flows through the capacitor C.
2 is not charged, and the other input terminal of OR circuit 2 is “0”
Therefore, a clock stop signal is obtained in which the output side of the OR circuit 2 becomes 1''.

Further, when the clock signal stops at +5V, the output from the first open collector NOT circuit 1 is "0".
'', that is, the first open collector NOT circuit 1 is in a closed state, and the current passing through the resistor R1 does not charge the capacitor CI, so one input terminal of the OR circuit 2 is @O''.

On the other hand, since the output side of the NOT circuit 3 becomes "0",
The input side of the second open collector NOT circuit 4 is “
0", the output side is "1", that is, this second open collector NOT circuit 4 is in an open state, capacitor C2 is charged to +5V through resistor R2, and the other input terminal of OR circuit 2 is "1". Therefore, a clock stop signal is obtained in which the output side of the OR circuit 2 becomes "1".

Note that when the clock signal is normal, the OR circuit 2
Since the time constants CIR+ and CzR2 of the capacitors CI and Cz and the resistors Rr and R2 connected to both input terminals are relatively large, the capacitor C+ is connected to the clock signal in which +5V and OV alternate in a short time.

C2 is never charged, both input terminals of the OR circuit 20 are always at “0”, and the output side of the OR circuit 2 is always at °0.
”, therefore, the clock stop signal that becomes “1” as described above cannot be obtained.

〔Example〕

FIG. 1 shows an embodiment of the clock signal stop detection circuit of the present invention, in which one side C3 of the clock signal CS is connected to a capacitor C1 whose one end is grounded via a first open collector NOT circuit 1. A circuit is formed such that it is applied to one input terminal of an OR circuit 2 connected to a resistor R1 to which a predetermined voltage +5V is applied, and the other clock signal C82 is connected to a NOT circuit 3 and a second open collector N. .

A capacitor C2 whose one end is grounded via a T circuit 4;
O connected to resistor R2 to which a predetermined voltage +5V is applied.
A circuit is formed such that the clock signal is applied to the other input terminal of the R circuit 2, and the clock signal from the output terminal of the OR circuit 2 is always a constant "1" regardless of whether it stops at 10'' or 1''. It is configured to obtain a state clock stop signal.

The purpose of obtaining a reset signal for resetting the operation of the digital control circuit based on the clock stop signal obtained by the clock signal stop detection circuit configured as described above is as follows.
As shown by the gi line, a comparator is connected to the clock stop signal via a third open collector NOT circuit 5 to a capacitor C1 whose one end is grounded and a resistor R1 to which a predetermined voltage +5V is applied. A circuit is formed such that the voltage is applied to one input terminal of the comparator 6, and a reference voltage is applied to the other input terminal of the comparator 6.

Next, the operation of obtaining a clock stop signal and a reset node signal for resetting the operation of the digital control circuit based on the clock stop signal by the circuit as described above will be explained.

For example, the clock signal alternates between +5v and Ov in a short period of time with an extremely accurate pulse width, and when the clock signal stops at OV, the output from the first open collector NOT circuit 1 is 1. '', that is, the first open collector NOT circuit 1 is in an open state, and the capacitor C3 is charged to +5V through the resistor R.
One input terminal of the OR circuit 2 becomes "1".

On the other hand, since the output side of the NOT circuit 3 becomes "1",
The input terminal of the second open collector NOT circuit 4 is “
1", the output side is "0", that is, this second open collector N0TIi14 is in a closed circuit state, and the resistor R2
Since the current passed through the capacitor C2 is not charged and the other input terminal of the OR circuit 2 becomes "0", a clock stop signal is obtained in which the output side of the OR circuit 2 becomes "1".

Further, when the clock signal stops at +5■, the output from the first open collector NoT circuit 1 is "0".
”, that is, the first open collector NOT circuit 1 is in a closed circuit state and the current passing through the resistor R3 does not charge the capacitor c1, so one input terminal of the OR circuit 2 is “0”.

On the other hand, since the output side of the NOT circuit 3 becomes "0",
The input terminal of the second open collector NOT circuit 40 is “
0” and the output side is “1”, that is, this second
The open collector NOT circuit 4 is in an open state, the capacitor c2 is charged to +5V through the resistor R2, and the other input terminal of the OR circuit 2 becomes "1", so the OR circuit 2
A clock stop signal whose output side becomes "1'" is obtained.

When the clock stop signal "1" obtained from the output side of the OR circuit 2 is applied to the input terminal of the third open collector NOT circuit 5, its output is "0", that is, this third Since the open collector NOT circuit 5 is closed and the current passing through the resistor R1 is not charged to the capacitor C1, one input terminal of the comparator 6 becomes "0".
'', and a reset signal for resetting the operation of the digital control circuit corresponding to the reference voltage is obtained from the output side of the comparator 6.

Note that when the clock signal is normal, the OR circuit 2
The time constants C, R,, C! of the capacitors C, , C, and resistors R, , R2 connected to the re-input terminal side of the ! Since R1 is relatively large, the capacitor C3°C2 is not charged by the clock signal in which +5V and Ov alternate in a short time, and the re-input terminal side of the OR circuit 2 is always "0". , the output side of the OR circuit 2 is always "O", and therefore the clock stop signal that is "1" as described above cannot be obtained.

〔Effect of the invention〕

Since this invention employs the lock signal stop detection circuit as described above, it is possible to always obtain a clock stop signal of a constant level regardless of whether the clock signal is stopped at a low level or a high level. By resetting the operation of the digital control circuit or the like based on this clock stop signal, it is possible to prevent the operation from running out of control or being damaged.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of a clock signal stop detection circuit according to the present invention. 1... first open collector NOT circuit, 2...
OR circuit, 3... NOT circuit, 4... second open collector NOT circuit, 5...
Third open collector NOT circuit, 6... Comparator, C1w C*, C3... Capacitor, RI, Rz
, R:l...resistance.

Claims (1)

[Claims] One of the clock signals is connected to the first open collector NOT
A circuit is formed in which a capacitor whose one end is grounded and a resistor to which a predetermined voltage is applied are connected through a circuit so that the clock signal is applied to one input terminal of an OR circuit, and the other end of the clock signal is applied to a NOT circuit. A circuit is formed such that the voltage is applied to the other input terminal of an OR circuit, which connects a capacitor with one end grounded and a resistor to which a predetermined voltage is applied, through a second open collector NOT circuit. 1. A clock signal stop detection circuit characterized in that the clock signal stop detection circuit is configured to always obtain a clock stop signal of a constant level from an output terminal of an OR circuit, regardless of whether the clock signal stops at a low level or a high level.