JPH02108154U - - Google Patents
Info
- Publication number
- JPH02108154U JPH02108154U JP1471389U JP1471389U JPH02108154U JP H02108154 U JPH02108154 U JP H02108154U JP 1471389 U JP1471389 U JP 1471389U JP 1471389 U JP1471389 U JP 1471389U JP H02108154 U JPH02108154 U JP H02108154U
- Authority
- JP
- Japan
- Prior art keywords
- program
- address
- stop
- contents
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000006870 function Effects 0.000 claims 2
Landscapes
- Debugging And Monitoring (AREA)
Description
図はこの考案のＲＯＭプログラムデバツグ装置
の一実施例を示す図であり、１は表示装置、２は
プログラム変更開始アドレス設定装置、３はプロ
グラムカウンタ、４はプログラム変更開始アドレ
ス保持レジスタ、５は第１の比較器、６は停止割
り込み発生装置、７はメモリ装置、８はレジスタ
、９は演算装置、１０はプログラム変更開始アド
レス設定装置、１１はメモリ書込み装置、１２は
プログラム変更開始アドレス保持レジスタ、１３
は第２の比較器、１４はプログラム実行アドレス
制御装置である。
The figure shows an embodiment of the ROM program debugging device of this invention, in which 1 is a display device, 2 is a program change start address setting device, 3 is a program counter, 4 is a program change start address holding register, and 5 is a program change start address holding register. A first comparator, 6 a stop interrupt generator, 7 a memory device, 8 a register, 9 an arithmetic unit, 10 a program change start address setting device, 11 a memory writing device, 12 a program change start address holding register , 13
1 is a second comparator, and 14 is a program execution address control device.
Claims (1)
ラムをデバツグするために、プログラム停止アド
レスを設定する停止アドレス設定装置と、この停
止アドレス設定装置から設定した停止アドレスを
保持する停止アドレス保持レジスタと、プログラ
ムの実行アドレスを保持するプログラムカウンタ
と、このプログラムカウンタの内容と上記停止ア
ドレス保持レジスタの内容の比較を行う第１の比
較器と、この第１の比較器からの比較信号を入力
し停止割り込みを発生する停止割り込み発生装置
と、プログラム変更開始アドレスを設定するプロ
グラム変更開始アドレス設定装置と、このプログ
ラム変更開始アドレス設定装置から設定したアド
レスを保持するプログラム変更開始アドレス保持
レジスタと、このプログラム変更開始アドレス保
持レジスタの内容と上記プログラムカウンタの内
容の比較を行う第２の比較器と、この第２の比較
器から比較信号を入力し、プログラムの実行アド
レスを制御するプログラム実行アドレス制御装置
と、プログラムの変更内容が書き込まれるメモリ
装置と、このメモリ装置にプログラムを書き込む
メモリ書込み装置と、演算を行う演算装置と、こ
の演算装置からの出力を保持するレジスタと、こ
のレジスタの内容及び上記メモリ装置の内容を表
示する表示装置を有するＲＯＭプログラムデバツ
グ装置において、ＲＯＭ上のプログラムの実行停
止させる機能及びＲＯＭ上のプログラムの内容を
変更させることと同等な機能を有することを特徴
としたＲＯＭプログラムデバツグ装置。 In order to debug a program on a ROM (read-only memory), there is a stop address setting device that sets the program stop address, a stop address holding register that holds the stop address set from this stop address setting device, and a stop address holding register that holds the stop address set by the stop address setting device. A program counter that holds an execution address, a first comparator that compares the contents of this program counter with the contents of the stop address holding register, and a comparison signal from this first comparator is input to generate a stop interrupt. a stop interrupt generator for setting a program change start address, a program change start address setting device for setting a program change start address, a program change start address holding register for holding the address set by this program change start address setting device, and a program change start address holding register for holding this program change start address. a second comparator that compares the contents of the register with the contents of the program counter; a program execution address control device that receives a comparison signal from the second comparator and controls the execution address of the program; and a program execution address control device that controls the execution address of the program. A memory device into which contents are written, a memory writing device which writes a program into this memory device, an arithmetic device which performs an operation, a register which holds the output from this arithmetic device, and a register which holds the contents of this register and the contents of the memory device. What is claimed is: 1. A ROM program debugging device having a display device for displaying information, the ROM program debugging device having a function of stopping execution of a program on the ROM and a function equivalent to changing the contents of the program on the ROM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1471389U JPH02108154U (en) | 1989-02-10 | 1989-02-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1471389U JPH02108154U (en) | 1989-02-10 | 1989-02-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02108154U true JPH02108154U (en) | 1990-08-28 |
Family
ID=31226162
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1471389U Pending JPH02108154U (en) | 1989-02-10 | 1989-02-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02108154U (en) |
-
1989
- 1989-02-10 JP JP1471389U patent/JPH02108154U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH02108154U (en) | ||
| JPH01151337U (en) | ||
| JPH02130041U (en) | ||
| JPH03113438U (en) | ||
| JPS6435438U (en) | ||
| JPH04148244A (en) | Software evaluating device | |
| JPS592056B2 (en) | Microcomputer program counter | |
| JPH01136251A (en) | Self-diagnosing system | |
| JPH01138143U (en) | ||
| JPS5815203U (en) | programmable controller | |
| JPS6452064U (en) | ||
| JPS6249463A (en) | Patching system of input output controller | |
| JPH01135554U (en) | ||
| JPH07113900B2 (en) | Emulation chip | |
| JPH0219932A (en) | Back-up device for development of microprocessor | |
| JPS6452061U (en) | ||
| JPS6082344U (en) | memory circuit | |
| JPH02120937A (en) | Information processor | |
| JPS62239242A (en) | Debugging device | |
| JPS5953410U (en) | Sequence control device | |
| JPH0373011B2 (en) | ||
| JPH0635742A (en) | Microcomputer equipment | |
| JPH0481939A (en) | Control system for microcomputer | |
| JPH01201730A (en) | Information processor | |
| JPH04305783A (en) | Microcomputer |