JPH0635742A - Microcomputer equipment - Google Patents

Abstract

(57) [Summary] [Purpose] It is possible to perform a read / write operation test on a RAM section without inputting an instruction and address information for the instruction from an external input / output interface section. Configuration: During a read / write operation test, the program counter control unit 21 outputs the output data of the program counter 15 to the address bus 18, and during a write operation test, the data polarity control unit 20 outputs the output data of the program counter 15. By outputting the polarity-converted data to the data bus 34, the output data of the program counter 15 is used as an address for the RAM section 16, and the polarity-converted data of the output data of the program counter 15 is used as the data for the RAM section 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer device having a function for executing a data read / write operation test for a built-in RAM section.

[0002]

2. Description of the Related Art In recent years, the use of microcomputer devices for various control of electrical equipment has become an indispensable element. Along with this, demands for functions and performances of microcomputer devices are becoming more sophisticated and complicated day by day. On the contrary, demands for development period and price are shorter and cheaper. Therefore, it is becoming important to test the function of the microcomputer device faster, easier, and not fail.

A conventional microcomputer device will be described below. FIG. 2 is a block diagram showing the configuration of a conventional microcomputer device. In FIG. 2, 1a
Is a program counter which counts up an address address indicating where instruction data is stored in the microcomputer device by one during one machine cycle of the microcomputer device.

Reference numeral 2a is a memory in which data can be freely read and written, and each memory cell is a RAM section for storing 1-bit information. Reference numeral 3a is a row coder that selects a memory cell in the row direction of the RAM section 2a by a signal of the address bus 4a. A column decoder 5a selects a memory in the column direction of the RAM section 2a by a signal of the address bus 4a.

Reference numeral 6a is a read / write control signal (not shown) for the RAM section 2a based on the RAM write signal 7a, the RAM read signal 8a, the RAM use selection signal 9a, and the system clock signal 10a of the microcomputer device. Is a RAM read / write timing control unit for generating Reference numeral 11a is a data bus of the microcomputer device, and 12a is a program counter control signal for controlling the count-up operation of the program counter 1a.

Reference numeral 13a is an input / output interface section for inputting an external signal to the address bus 4a and the instruction bus 14a of the microcomputer device and outputting it to the outside. Hereinafter, the operation of the conventional microcomputer device configured as described above will be described.

Normally, RA during microcomputer operation
The data read / write operation to the M section 2a is controlled by the RAM write signal 7a, the RAM read signal 8a, the RAM use selection signal 9a and the system clock signal 10a. At the time of writing to the RAM section 2a, the RAM read signal 8a becomes inactive and the RAM write signal 7
a and the RAM use selection signal 9a are activated, and each signal is generated in synchronization with the system clock signal 10a.

Further, at the time of reading to the RAM section 2a,
The RAM write signal 7a becomes inactive, the RAM read signal 8a and the RAM use selection signal 9a become active, and each signal is generated in synchronization with the system clock signal 10a. Then, these RAM read signals 8
a, the RAM write signal 7a and the RAM use selection signal 9a are generated when the microcomputer device receives an instruction to access the RAM section 2a.

In such a microcomputer device, in order to perform a data read / write test with respect to the RAM section 2a, the microcomputer device is set to an operation mode for a functional test. When this operation mode is set, the microcomputer device once enters the initial state and then starts operating. As a result, the initial value of the program counter 1 is set to "0".

In this operation mode, the microcomputer device does not use the instruction data stored in the internal memory, and the program counter 1
The a does not output the address signal for accessing the instruction data to the address bus 4a. That is,
The program counter 1a is prohibited from counting up by the program counter control signal 12a, and
The output operation is also prohibited so that unnecessary data is not output to the address bus 4.

As a result, the microcomputer device is
An instruction and address information of the instruction can be given from the outside through the input / output interface section 36a, a functional operation test of the microcomputer device can be arbitrarily performed, and a data read / write test with respect to the RAM section 2a can be performed. You can

[0012]

However, in the conventional microcomputer device configured as described above, when a data read / write operation test is performed on the RAM unit 2a, the RAM unit is executed by an instruction executable by the microcomputer unit. It was necessary to perform a data write operation and a data read operation to 2a.

That is, when performing a data read / write operation test on the RAM section 2a, the internal instruction data is synchronized with the address bus 4a from the outside via the input / output interface 13a, in synchronization with the system clock signal 10a of the microcomputer device. Address information of the instruction is input at the timing of outputting the address signal of the
It was necessary to input the instruction data to the instruction bus 14a via 3a at the timing when the internal instruction data outputs the data to the instruction bus 14a. Furthermore, the RAM section 2
Since it is necessary to perform a write test and a read test on all the cells of a, an instruction and the address information of the instruction are externally supplied until the writing or reading of the data at the address addresses of all the cells of the RAM section 2a. I had to keep giving. Therefore, in order to realize this, there is a problem that a measuring device of a certain scale or a dedicated evaluation device must be prepared.

Further, since the data writing time and the data reading time with respect to the RAM portion 2a are determined by the execution time of the instruction used for the data writing operation and the data reading operation with respect to the RAM portion 2a, when the execution time of the instruction itself is long. However, there is a problem that the data writing time and the data reading time become long. An object of the present invention is to solve the above-mentioned conventional problems, and to perform a read / write operation test on a RAM section without inputting an instruction and address information for the instruction from the outside through an input / output interface section. It is to provide a microcomputer device capable of performing the above.

[0015]

A microcomputer device according to the present invention comprises a program counter control section and a data polarity control section. The program counter control unit outputs a read / write control signal to the RAM unit, and outputs the output data of the program counter to the address bus during a data read / write operation test on the RAM unit. The data polarity control unit converts the polarity of the output data of the program counter and outputs it to the data bus during the data write operation test for the RAM unit based on the data polarity control signal output from the program counter control unit. Is.

[0016]

According to the structure of the present invention, during the read and write operation tests, the program counter control section outputs the output data of the program counter to the address bus, and during the write operation test, the data polarity control section controls the program counter output. By outputting the data whose polarity has been converted to the data bus, the output data of the program counter is used as an address for the RAM section,
Data obtained by converting the polarity of the output data of the program counter can be used as the data for the RAM section. Therefore, the read / write operation test for the RAM section can be performed at the timing of the count-up operation of the program counter using the output data of the program counter.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a microcomputer device according to an embodiment of the present invention. In FIG. 1, reference numeral 15 is a program counter which counts up the address address of the program to be executed by one during one machine cycle of the microcomputer device.

Reference numeral 16 is a memory in which data can be freely read and written, and each memory cell is a RAM section for storing 1-bit information. A row decoder 17 selects a memory cell in the row direction of the RAM section 16 based on a signal on the address bus 18. A column decoder 19 selects a memory cell in the column direction of the RAM section 16 based on a signal on the address bus 18.

20 is a program counter data bus 30
A data polarity control unit that controls the polarity and output of the above data. A program counter control unit 21 receives data from the program counter 15 via the original program counter data bus 22, and receives a program counter output control signal 26, an original RAM write signal 23, and an original RAM read signal 24 from the microcomputer device. Also, the original RAM use selection signal 25 is input, and the program counter output control signal 26 causes the RAM write signal 27 and the RAM read signal 28 at new timing.
And a RAM use selection signal 29, and output data of the program counter 15 to the address bus 18,
In addition, the data polarity control unit 20 has a program counter 1
The data polarity control signal 31 for controlling whether to change (or invert) the polarity of the output data of No. 5 is output.

Reference numeral 32 denotes a RAM read / write timing control unit, which includes a RAM write signal 27 and a RAM read signal 2
8 and a RAM use control signal 29 and a system clock signal 33, a read / write control signal (not shown) for executing a read / write operation of the RAM section 16 is output. Reference numeral 34 is a data bus, and 35 is RAM write data output from the data polarity controller 20.

Reference numeral 36 is an input / output interface unit for inputting signals to the address bus 18 and instruction bus 37 from the outside and outputting them to the outside. 38 is a count control signal for controlling the operation of the program counter 15. The operation of the thus configured microcomputer device will be described below.

First, a normal microcomputer operation will be described. The microcomputer device is RA
When an instruction for data access to the M section 2 is executed, an original RAM write signal 23, an original RAM read signal 24 and an original RAM use control signal 25 are generated. Based on the program counter output control signal 26, the program counter control section 21 writes the original RAM write signal 23,
Without changing the original RAM read signal 24 and the original RAM use control signal 25, the RAM write control signals 27, R
AM read control signal 28 and RAM use selection signal 2
9, and outputs to the RAM read / write timing control unit 32.

Further, the program counter controller 21 is
A count control signal 38 for instructing the program counter 15 to count up is output. Further, the program counter control unit 21 causes the output data of the program counter 15 on the original program counter data bus 22 to be output to the address bus 18 without changing.

Further, the program counter controller 21
Outputs the output data of the program counter 15 to the data polarity control unit 20 and at the same time outputs the data polarity control unit 20.
The data polarity control signal 31 is output to. At this time, the data polarity control signal 31 output from the program counter control unit 21 instructs the data polarity control unit 20 not to generate an output signal for the input signal. As a result, the data polarity controller 20 does not output a signal to the data bus 34.

As described above, during normal microcomputer operation, the program counter control unit 21 changes the output data of the program counter 15, the original RAM write signal 23, the original RAM read signal 24 and the original RAM use control signal 25. Address bus 1 without
8 and the RAM read / write timing control unit 32,
Moreover, by not outputting a signal from the data polarity control unit 20, a normal microcomputer operation is performed.

Next, when the microcomputer device is set to the operation mode for the function test, the program counter control section 21 can be set to three operation states.
The switching of the operation state of the program counter control unit 21 is performed through the initial state of the microcomputer device. As a result, when the operating state of the program counter control unit 21 is switched, the initial value of the program counter 15 becomes "0".

Below, the program counter controller 21
The two operating states and will be described. The operating state is a state for a functional test of the microcomputer device. At this time, the microcomputer device does not use the instruction data stored in the internal memory, and the program counter 15 does not generate the data for accessing the instruction data.

That is, the program counter controller 21
Inhibits the count-up operation of the program counter 15 by the count control signal 38 generated based on the program counter output control signal 26, and inhibits the program counter 15 from outputting unnecessary data. The program counter control unit 21 also prohibits the output of a signal from the data polarity control unit 20 to the data bus 34 by the data polarity control signal 31. Further, the program counter control unit 21 determines the original RAM write signal 2 based on the program counter output control signal 26.
3, RAM write control signal 2 without changing the original RAM read signal 24 and the original RAM use control signal 25
7, RAM read / write timing control section 32 as RAM read control signal 28 and RAM use selection signal 29
Output to.

As a result, in the microcomputer device,
It is possible to give an instruction and address information of this instruction from the outside through the input / output interface section 36, and it is possible to arbitrarily test the functional operation of the microcomputer device. In this way, in the operating state, the program counter controller 21 causes the program counter 15 to
And the output from the data polarity control unit 20 to the data bus 34 are prohibited, and the RAM read / write timing control unit 32 receives the original RAM write signal 23, the original RAM read signal 24, and the original RAM use control signal 25. Similar R
AM write control signal 27, RAM read control signal 2
8 and the RAM use selection signal 29 are output, it becomes possible to input a command and address information of the command to the microcomputer device from the outside through the input / output interface section 36, and thereby the function of the microcomputer device. The operation test can be arbitrarily performed.

Next, the operation state is a state of a data writing operation test to the RAM section 16 using the output data of the program counter 15. At this time, an instruction and address information of this instruction are not input from the outside through the input / output interface unit 36 as in the operation state for the functional test of the microcomputer device described above. However, in the initial state when switching to this operating state, the program counter 15 is the same as the operating state.
The count-up operation of is disabled.

The program counter controller 21 is a RAM
The read / write timing control unit 32 is set to the active state R.
The AM write signal 27 and the RAM use selection signal 29 are output, and the RAM read signal 2 in the inactive state is output.
8 is output. This RAM write signal 27 and RA
The output waveform of the M use selection signal 29 is one write cycle in the same cycle as the program counter 15 counts up by one. As a result, the program counter control unit 21 outputs to the RAM read / write timing control unit 32 a signal effective only for writing data to the RAM unit 16.

The program counter 15 has an initial value "0" immediately after switching from an arbitrary operation to an operating state.
Has stopped. Therefore, the program counter control unit 21 outputs the count control signal 38 instructing the program counter 15 to start the count-up operation. In addition, the program counter control unit 2
1 is based on the program counter output control signal 26,
The output data of the program counter 15 on the original program counter data bus 21 is output on the address bus 18 via the program counter data bus 30. At this time, the program counter control unit 21 to the data bus 18
The output tanming of the signal to the upper side is R in normal operation.
The timing is the same as the timing of outputting the address signal for the data writing operation to the AM section 16 onto the address bus 18. Therefore, on the address bus 18, a signal is output from the program counter 15 which is incremented by one every machine cycle of the microcomputer device.

Further, the program counter controller 21 is
The output data of the program counter 15 is output to the data polarity control unit 20 as well as the address bus 18 via the program counter data bus 30. Then, the program counter control unit 21 outputs the data polarity control signal 31 to the data polarity control unit 20 to output the data on the program counter data bus 30 without changing, or
Instruct whether to change the polarity of data and output. As a result, the data polarity control unit 20 causes the data bus 34 to
The RAM write data 35 is output at the same timing as the normal write data for the RAM section 16 is output to the data bus 34.

In this way, in the operating state, the program counter control section 21 starts the count-up operation of the program counter 15, and outputs the signal output from the program counter 15 to the original program counter data bus 22 to the address bus 18 and Output to the program counter data bus 30. Then, the data polarity controller 2
0 indicates the program counter 1 based on the data polarity control signal 31 output from the program counter controller 21.
The polarity of the output data 5 is converted and output on the data bus 34.

As described above, the output data of the program counter 15 is used as the address of the write operation to the RAM section 16, and the data polarity control section 20 converts the polarity of the output data of the program counter 15 to the RAM section 16 to write the data. I / O interface unit 3 from the outside
It is possible to perform a data write test to the RAM section 16 for each count-up operation of the program counter 15 without inputting an instruction and address information for the instruction via 6.

Finally, the operation state is a data read operation test state to the RAM section 16 using the output data of the program counter 15. At this time, an instruction and address information of this instruction are not input from the outside through the input / output interface unit 36 as in the operation state for the functional test of the microcomputer device described above. In addition, in the initial state when switching to this operating state, the count-up operation of the program counter 15 is prohibited as in the operating state. However, the data on the data bus 34 can be output to the outside through the input / output interface section 36.

The program counter control unit 21 is a RAM
The read / write timing control unit 32 is set to the active state R.
The AM read signal 28 and the RAM use selection signal 29 are output, and the RAM write signal 2 in the inactive state is output.
7 is output. This RAM read signal 28 and RA
The output waveform of the M use selection signal 29 is one read cycle in the same cycle as the program counter 15 counts up by one. As a result, the program counter control unit 21 outputs to the RAM read / write timing control unit 32 an effective signal only for reading data from the RAM unit 16.

Further, similarly to the operating state in the write mode, the program counter 15 stops at the initial value "0" immediately after switching from an arbitrary operation to the operating state. Therefore, the program counter control unit 2
1 outputs a count control signal 38 instructing the program counter 15 to start a count-up operation.

Further, the program counter controller 21 is
Based on the program counter output control signal 26, the output data of the program counter 15 is output onto the address bus 18 via the program counter data bus 30. The output timing of the data from the program counter control unit 21 to the data bus 18 at this time is the same as the timing of outputting the address signal for the data read operation to the RAM unit 16 on the address bus 18 in the normal operation. Is. Therefore, on the address bus 18, the signal of the program counter 15 which is incremented by one every one machine cycle of the microcomputer device is output.

Further, the program counter controller 21 is
The output data of the program counter 15 is output to the data polarity control unit 20 as well as the address bus 18 via the program counter data bus 30, but in the operation state of this data read operation, the data polarity of the program counter control unit 21 is changed. The control signal 31 controls the data polarity controller 20 so that the data on the program counter data bus 30 is not output to the data bus 34.

In this way, in the operating state, the program counter control section 21 starts the count-up operation of the program counter 15, and outputs the signal output from the program counter 15 to the original program counter data bus 22 to the address bus 18 and Output to the program counter data bus 30. At this time, the data polarity control unit 2
0 does not output the data on the program counter data bus 30 to the data bus 34 based on the data polarity control signal 31 output from the program counter control unit 21.

By using the output data of the program counter 15 as an address for the read operation to the RAM section 16 as described above, it is possible to prevent an instruction and address information for the instruction from being input from the outside through the input / output interface section 36. , The data written in the RAM writing mode from the address 0 to all addresses of the RAM section 16 are read by the program counter 1 from the address 0 to the address 2 of the RAM section 16.
It becomes possible to read the data in the RAM section 16 to the data bus 34 in the order of the address addresses indicated by the output data by the count-up operation of 5, and the data is read from the RAM section 16 for each count-up operation of the program counter 15. The test can be conducted.

As described above, according to the embodiment, the program counter control unit 21 outputs the output data of the program counter 15 to the address bus 18 during the data read / write operation test, and the data polarity control during the write operation test. By outputting the data, which has the polarity of the output data of the program counter 15 converted by the unit 20, to the data bus 34, the output data of the program counter 15 is used as an address for the RAM unit 16, and the polarity of the output data of the program counter 15 is converted. The created data can be used as data for the RAM unit 16.

Therefore, the read / write operation test for the RAM 16 is performed by the program counter 15
Can be performed at the timing of the count-up operation of the program counter 15 using the output data of. As a result, it is possible to perform a read / write operation test for the RAM section 16 without externally supplying an instruction and address information for the instruction as in the conventional case.

Further, by using the output data of the program counter 15 as an address and data for the RAM section 16, one data is read in one count-up time of the program counter 15 without depending on the instruction execution time of the microcomputer device. And can write.

[0046]

According to the microcomputer device of the present invention, during the read and write operation tests, the program counter control section outputs the output data of the program counter to the address bus by the data polarity control section, and during the write operation test. , The data output from the program counter is converted into the RA by outputting the data whose polarity is converted to the data bus.
The address for the M section can be used, and the data obtained by converting the polarity of the output data of the program counter can be used as the data for the RAM section. Therefore, the read / write operation test for the RAM section can be performed at the timing of the count-up operation of the program counter using the output data of the program counter.

As a result, it is possible to perform a read / write operation test for the RAM section without externally supplying an instruction and address information for the instruction as in the conventional case. Also, the output data of the program counter is stored in RAM
By using it as an address and data for a part,
It is possible to read and write one data in one count-up time of the program counter without depending on the instruction execution time of the microcomputer device.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a microcomputer device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional microcomputer device.

[Explanation of symbols]

 15 program counter 16 RAM section 18 address bus 20 data polarity control section 21 program counter control section 31 data polarity control signal 34 data bus

Claims (1)

[Claims] 1. A RAM section is used to specify an address by a signal on an address bus and data by a signal on a data bus, and read and write operations of the data to and from the RAM section based on a read / write control signal. A program for executing the microcomputer device, which outputs the read / write control signal to the RAM unit, and outputs output data of a program counter to the address bus during a data read / write operation test on the RAM unit. Based on the counter control unit and the data polarity control signal output from the program counter control unit, the polarity of the output data of the program counter is converted and output to the data bus at the time of the data write operation test to the RAM unit. Data polarity Microcomputer device and a control unit.