JPH021085A - data input device - Google Patents

Abstract

PURPOSE:To make an input pin into a multifunctional input pin and to miniaturize and LSI by inputting input signals to be discriminated by a desired threshold voltage to the same input pin and deciding and reading the input signals with two or more types of deciding values. CONSTITUTION:For a signal input external terminal IP, address switches S1-Sn are respectively connected between the output terminals of plural input buffers VTH1-VTHn having different threshold voltages with each other and data bus BUS in the LSI. For these switches S1-Sn, a desired switch out of them is switch- controlled according to the program of a microcomputer. For example, when a data signal to make a line l8 into H is outputted to an address bus ABUS, and next, a read control signal is supplied to a terminal W of a register RG, the data are read to the register RG, and a decoder circuit DEC decodes the read data and makes the line l8 into H. Thus, the switch is turned on, the signal, the level of which is discriminated by the desired threshold voltage, is transferred to the bus BUS and read to a memory, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data input device for a logic circuit, and particularly to a data input device for a one-chip microcomputer.

In a one-chip microcomputer, circuit elements for configuring its arithmetic unit (CPU), memory, input/output unit, etc. are configured on one semiconductor substrate using known LSI technology. This human power section is normally configured to input a human power signal by regarding it as a binary signal. In this case, the logic threshold voltage at the input section is set to a fixed level of an appropriate value, such as a level for determining the signal level output from a transistor-transistor logic circuit.

However, in order to enable the microcomputer to be used in a variety of applications, the input section can be configured to take on different logic threshold voltages, thereby providing a variety of signal generators. F It is desirable that the signal output from the starting device can be input.In this case, the microcomputer configured as an LSI should be configured so that its external terminals are not increased. It is preferable to

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a data input device for a logic circuit that is capable of discriminating an input signal supplied through a single input external terminal using two or more types of logic threshold voltages. It is in.

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 1 is a circuit block diagram of one embodiment of the present invention.

In the same figure, D. Indicators are external terminals for signal input of the LSI constituting the microcomputer.

The external terminal D0 includes an inverter circuit IV.

and IV, an input buffer B P consisting of
The input terminal of the converter C'MI' and the non-inverting input terminal of the converter C'MI' are connected.

The output terminal of the input buffer BP is connected to the address bus BU via a switch 810 composed of an insulated gate field effect transistor (MISFET).
It is connected to the line t0 that constitutes S.

Similarly, the output terminal of the core/F-lator CMP is connected to the line t0 via a switch 32G made up of a MISFET.

The external terminal is connected to an inverter circuit IV.

and an input buffer BP composed of
, and the non-inverting input terminal of the converter CM Pa are connected. Input buffer 7 above
The output terminals of BPa and converter CMP are connected to data bus BU via switches Sta and 826, respectively.
S1? It is commonly connected to the line t6 formed by M.

The inverting input terminals of the converters CMPO to CMPa are connected to external terminals.

The above external terminals also have inverter circuits IV,...
and I V2. Ingt buffer BP composed of
The input terminal of the camera is connected.

The output terminal of the input buffer BP is switch 8.
1? The line t constituting the data bus 13Us is connected to the line t via the line t.

Ingt buffer BP mentioned above, no LBP? Switch 8.0 or St? connected to the CD output terminal. have their control terminals, ie, gate a poles, commonly connected to line t.

Similarly, the above components C”MPO to CMP6
A switch S, connected to the output terminal of. to Sta are commonly connected to line t9.

The line t8+t is connected to the output terminal of the decoder circuit DEC to which the output signal of the register G is supplied.

The registers R and G have an input terminal connected to the address bus ABUS, a terminal W to which a data read control signal is supplied, and a terminal to which a reset signal is supplied. The terminal W and the box are supplied with the signal from a control circuit (not shown).

In this embodiment, although not particularly limited, the input buffer BP or BP has a logic threshold voltage that determines the signal level output from a known transistor-transistor logic (TTL) circuit. Be matched with the level to do.

In addition, the upper level of the player's income is 3P0 or BP.
For example, as shown in FIG. 2, each inverter circuit for configuring y is composed of a load MISFET Q in a denomination mode whose gate and source are connected, and a drive MISFET Q2 in an enhancement mode. configured. For an inverter circuit like the one shown, its logic threshold voltage is the load MI8FETQ+
This can be changed by changing the relative size of tJhMIsFETQ2(7)1111.

The above converter CMP, no LC'MI'6 (7
) each has a configuration as shown in FIG. 13, for example.

Figure 3: MISFETQ! A first stage differential amplifier circuit is configured by Q7 and M I 8 F
A second stage differential amplifier circuit is configured by ETQ8 to Q10. In the superfertilization first stage differential amplifier circuit,
Although not particularly limited, MISFETQ is driven by a reverse pulse CP.

As a result, the connogrator of FIG. 3 is activated when the clock signal CP is supplied.

In addition, in FIGS. 1 to 3, each MISF
ET is assumed to be of n-channel type. A degradation mode MISI"ET like Ql has a different symbol from an enhancement mode MTSFET like Q2.

According to the embodiment of FIG. 1, the input signals supplied to external terminals D0 to B7 are connected to respective in/2 node buffers BP. The respective levels are determined by BP to BP, and the input signals supplied to Do to B6 of the external terminals Do to B7 are respectively connected to the corresponding comparators CMP. Or CM I'. Each level is determined by IIC.

The input buffers BP0 to B1)7 or the comparators CMPo to C+VIP.

One output word is transferred to the internal data bus BUS as the switches SIG to S17 or S2o to S26 are controlled according to the microcomputer program.

For example, the external terminal mentioned above. First, when the output terminal of a TTL circuit or a circuit (not shown) with output characteristics similar to that is connected, the data signal for raising the level of Hta to a high level is first sent to a memory or register (not shown). It is output from address bus ABUS.

Next, a read control signal is supplied to the terminal W of the register G. As a result, the data on the AT9 address bus is read into the registers R and G. The decoder circuit DEC decodes the output signal of the register G and makes the line 1 high.

The switch SIO to 817 is turned on by the high level signal at 4%l/=, and as a result, the output fy of the input buffer BP to BP is turned on.
The number is the corresponding line t of the data bus B [JS. or t7
supplied to

The signal supplied to the data bus BUS is read into a register or memory (not shown).

Next, a reset signal is supplied to the terminal of the register G. In response, the signal being supplied from the decoder circuit DEC to the line t is returned to low level,
The above switch S1° to 81? is turned off.

The above switch S10 to 81? is turned off, the input buffer BP or BP
, and the data bus +3 US are electrically separated. As a result, the above data bus B [JS,
This allows it to be controlled by another circuit (not shown).

When transferring the output signal of the comparator CMP or C'MP to the data bus BUS, similarly, 1, tot
The data signal to make o high level is sent to register R.
Just let GK set. In this case, an appropriate bias circuit is provided outside the LSI, and the voltage output from this bias circuit is set as the logic threshold voltage.
Comparator CMPo or CM via external terminal
This will be supplied to the inverted input chanter of Pe.

Note that the non-inverting input terminal of LCMP6 without the comparator CMPo may be supplied with not only a binary signal but also an analog signal output from an analog circuit such as a temperature detection circuit using a thermistor. can. Therefore, an LSI microcomputer equipped with the input device shown in FIG. 1 can be used in a wide variety of applications.

The human powered device of FIG. 1, as described above, requires fewer external terminals.

FIG. 4 is a block diagram of another embodiment of the present invention.

In the same figure, the input terminals of several input buffers VTIII to V7on having different threshold voltages are commonly connected to the external terminal IP for signal input, and the input terminals of the input buffers Vtul to V7on are commonly connected to each other.
VTIIn output terminal and I, SI internal data bus BU
and an address switch S between each.

~S0 is connected. In this example, the switch S
A desired one of the desired SBs is switch-controlled by the same method as in the previous embodiment.

As a result, a signal whose level is determined based on a desired threshold voltage is transferred to the data bus BUS.

FIG. 5 shows another embodiment of the present invention, in which comparators CMP to CMPfi are used in place of input buffers Vtn1 to VTIIm in FIG. 4.

According to the embodiments shown in FIGS. 4 and 5, there is no need to provide a circuit for forming a threshold voltage outside the LSI.

As explained above, according to the present invention, input signals to be discriminated based on a desired threshold voltage are
Since input to the ST input pin (external terminal) allows human input signals to be judged and read using two or more types of judgment values, the input pins of the LSI can be made multi-functional, and the LSI can be made smaller.

[Brief explanation of the drawing]

? Figure A'rJ1 is a diagram showing an example of a data input device for a logic circuit in an actual example, Figure 2 is a circuit diagram of an inverter circuit, Figure 3 is a circuit diagram of a comparator, and Figure 4 is a diagram of this book. FIG. 5 is a diagram showing the structure of still another embodiment of the present invention. DO-D, , I 1)...Input bin, BPo
-BF2. V T II l~V〒Ila...Input in park, 81~SI,...Switch, BUS...LS
I internal data bus, CMPo to 4pH... comparator.ぢ 4 Concave height 5 Snake

Claims (1)

[Claims] 1. A data input device for a microcomputer, comprising a comparator circuit that determines the level of an input signal supplied via an external terminal, and the comparator circuit operates according to a pulse signal. A data input device characterized in that its state is controlled. 2. The comparator circuit includes an input MISFET that discriminates the input signal level, and a switch MISFET connected in series with the input MISFET and switched by the pulse signal. The data input device according to item 1.