JPH0210868A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To accelerate a logic circuit by alternately disposing lines of inner cells composed only of complementary MOS elements and lines of inner cells composed only of bipolar elements on an inner cell region. CONSTITUTION:An IC chip has an inner cell line 3 composed only of pad 1, input/output cell 2 and bipolar element, and an inner cell line 4 composed only of complementary MOS element. Thus, a logic circuit is composed only of the MOS element for a low load capacity, and a logic circuit of 2-stage configuration of the MOS element and the bipolar element is composed for a high load capacity. Accordingly, a high speed logic circuit which utilizes the advantages of both can be obtained.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit device.

[Conventional technology]

In a conventional semiconductor integrated circuit device using a gate array method in which a logic circuit is constructed using complementary MOS elements and bipolar elements, the internal cell area has a two-stage structure with a complementary MOS element in the output stage and a bipolar element in the output stage. , and they were arranged in rows and columns with each cell as one internal cell.

[Invention or problem to be solved]

In the semiconductor integrated circuit device using the gate array method in which a logic circuit is constructed from conventional complementary MOS elements and bipolar elements as described above, it has a two-stage configuration with a complementary MO8 element in the input stage and a bipolar element in the output stage. They are arranged in rows and columns as one cell, and the increase in the transmission delay time t with respect to the load capacitance Ct is greater than that of a gate array composed only of complementary MOS elements due to the high driving ability of the bipolar elements in the output stage. In other words, the increase in the transmission delay time tpa for heavy load capacitance CL can be reduced, and high-speed operation can be achieved. However, because it has a two-stage configuration of complementary MOS elements and bipolar elements, the transmission delay time tpd is said to be larger for small load capacitance CL than a gate array in which the logic circuit is composed of only complementary MOS elements. There are drawbacks.

An object of the present invention is to provide a semiconductor integrated circuit device that solves the above problems.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a gate array type semiconductor integrated circuit device in which a logic circuit is configured with complementary MO8 elements and bipolar elements, in which a row of internal cells consisting only of complementary MOS elements is provided in an internal cell region. and rows of internal cells composed only of bipolar elements are arranged alternately.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. This IC chip has a pad 1, an input/output cell 2, an internal cell row 3 consisting only of bipolar elements, and an internal cell row 4 consisting only of complementary MO8 elements. Note that the wiring area is included in rows 3 and 4, or both rows 3 and 4. In a conventional gate array in which complementary MO8 elements and bipolar elements are mixed, the increase in transmission delay times t and d with respect to heavy load capacitance CL can be reduced, and the gate array can operate at high speed. However, since the internal cell has a two-stage configuration of complementary MOS elements and bipolar elements, complementary MOS
The propagation delay time j pd is longer than that of a gate array in which a logic circuit is constructed only from elements.

Therefore, with the above configuration, a logic circuit with only complementary MOS elements is configured for low load capacity, and a two-stage logic circuit of complementary MOS elements and bipolar elements is configured for high load capacity. If the configurations are different, a high-speed logic circuit that takes advantage of both advantages can be realized.6 [Effects of the Invention] As explained above, the present invention provides cell rows composed only of complementary MOS elements and cell rows composed only of bipolar elements. By arranging , the transmission delay time d can be made smaller than that of an IC chip using a gate array type semiconductor device in which a two-stage configuration of a complementary MO8 element and a bipolar element is arranged in rows and columns as one cell, resulting in a lower load. For capacitance, a logic circuit can be constructed using only complementary MO8 elements, and for high load capacitance, a two-stage logic circuit consisting of complementary MOS elements and bipolar elements can be constructed, resulting in a high-speed logic circuit. have an effect.

[Brief explanation of the drawing]

FIG. 1 is a plan view of an IC chip showing an embodiment of the present invention. ■... Pad 2... Input/output cell 3... Internal cell row 4 with only bipolar element cells...
Internal cell row patent applicant with only complementary MOS device cells
NEC Corporation Figure 1

Claims (1)

[Claims] (1) In a gate array type semiconductor integrated circuit device in which a logic circuit is composed of complementary MOS elements and bipolar elements, an internal cell row composed only of complementary MOS elements and a row of internal cells composed only of bipolar elements is arranged in the internal cell area. A semiconductor integrated circuit device characterized in that rows of internal cells are arranged alternately.