JPH0210972A - Picture-in-picture memory - Google Patents

Abstract

PURPOSE:To prevent blur of color by outputting a sampling clock D/A- converting three signals, R-Y, B-Y, Y simultaneously at the changeover of a frame data and a slave screen video signal from picture-in-picture. CONSTITUTION:When a picture-in-picture memory 2 outputs respectively a frame data and a slave screen video signal, the phase of the leading of a sampling clock 3 of a D/A converter 40 of the R-Y, B-Y and Y signals is deviated the same as a conventional system. However, a color blur correction circuit 30 matches the leading phase of the sampling clock 3 of the D/A converter 40 of the signals R-Y, B-Y, Y at the switching of the frame data and the slave pattern video signal. Thus, the switching of the output signal 5 of the D/A converter 40 is outputted without mixed signal and the effect of preventing blur of color is attained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a picture-in-picture memory, particularly a frame data built-in as a part of a small screen signal, and a method for switching between the frame data and the small screen video signal. This invention relates to a picture-in-picture memory that outputs the sampling clock of an A converter so that there is no color blurring.

[Conventional technology]

The conventional picture-in-picture memory converts the small screen output signal into a D/A as shown in the timing diagram of Figure 3.
Three sampling clocks (RY,
B-Y, Y) was being output.

However, when outputting or switching frame data and small screen video signals, the rising phase of the sampling clock of the D/A converter when converting data output from memory into D/A is the writing order of the small screen video signal. Therefore, the D/A converter output signal is shifted by the phase shift of the rising edge of the sampling clock.
The sub-screen video signals of the frame data were mixed together, causing color blurring.

[Problem to be solved by the invention]

In the conventional picture-in-picture memory described above, the output phases of the sampling clocks of the D/A converters for the three small screen signals are shifted at the switching point between the frame data and the small screen video signal. There is a drawback that color bleeding occurs due to the time lag.

[Means to solve the problem]

The picture-in-picture memory of the present invention incorporates a frame data component signal, outputs three sampling clocks for D/A conversion when reading the frame data component signal and the small screen video component signal, and outputs three sampling clocks for D/A conversion, and The configuration is such that the output phases of the three sampling clocks are aligned when switching between the video component signal and the frame data signal.

〔Example〕

The present invention will be described in detail below using the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a timing diagram.

When frame data and sub-screen video signals are being output, the rising phases of the sampling clocks 3 of the R-Y, B-Y, and Y D/A converters 40 are shifted as in the conventional case, but the frame data When switching between the sub-screen video signal and the sub-screen video signal, the color fringing correction circuit 30
The rising phase of the sampling clock 3 of the Y D/A converter 40 is matched. As a result, D/A
Even when the output signal 5 of the converter 40 is switched between the frame data and the small screen video signal, the signals are output without being mixed.

〔Effect of the invention〕

As explained above, the present invention uses a sampling clock that simultaneously D/'A converts the three signals R-Y, B-Y, and Y when switching between the frame data and the sub-screen video signal. - Outputting from a picture has the effect of preventing color bleeding.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram when the present invention is used, and FIG. 3 is a timing diagram showing a conventional example. DESCRIPTION OF SYMBOLS 1... Small screen signal, 2... Picture-in-picture memory, 3... D/A converter sampling clock, 4... Picture-in-picture memory output small screen signal, 5... ...Small screen output signal, 6
...PIP memory output (RY) data, 7...P
IP memory output (B-Y) data, 8... PIF memory output (Y) data, 9... D/A converter (R-
Y) Sampling clock, 10...D/A converter (B-Y) sampling clock, 11...D/'
A converter (Y) sampling clock, 12...
D/A converter (RY) output data, 13...D
/A converter (B-Y) output data, 14...D/
A converter (Y) output data, 15...PIP memory output (R-Y) data, 16...PIP memory output (B-Y) data, 17...PIP memory output (Y)
data, 18...D/A converter (RY) sampling clock, 19...D/A converter (B-Y
) sampling clock, 20... D/A converter (Y) sampling clock, 21... D/A converter (RY) output data, 22... D/A converter (B-Y) output data, 23...D/A converter (Y) output data.

Claims (1)

[Claims] It has a built-in frame data component signal, outputs three sampling clocks for D/A conversion when reading this signal and the small screen video component signal, and when switching between the small screen video component signal and the frame data signal. A picture-in-picture memory characterized in that it is configured so that the output phases of three sampling clocks are aligned.