JPH02113338U - - Google Patents
Info
- Publication number
- JPH02113338U JPH02113338U JP2262289U JP2262289U JPH02113338U JP H02113338 U JPH02113338 U JP H02113338U JP 2262289 U JP2262289 U JP 2262289U JP 2262289 U JP2262289 U JP 2262289U JP H02113338 U JPH02113338 U JP H02113338U
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- semiconductor chip
- metal wire
- thin metal
- conductor pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000000919 ceramic Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図は、本考案の一実施例による半導体装置
の縦断面図である。第２図は、従来の半導体装置
の縦断面図である。
１……樹脂、２……セラミツク基板、３……半
導体チツプ、４……金属細線、５……外部リード
、６……導体パターン、７……空洞。
FIG. 1 is a longitudinal sectional view of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a longitudinal cross-sectional view of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1...Resin, 2...Ceramic substrate, 3...Semiconductor chip, 4...Metal thin wire, 5...External lead, 6...Conductor pattern, 7...Cavity.
Claims (1)
洞を有するセラミツク基板と、該セラミツク基板
上の前記導体パターン上に搭載された半導体チツ
プと、該半導体チツプの電極と前記セラミツク基
板上の他の導体パターンとを接続する金属細線と
、前記半導体チツプと前記金属細線とを覆つて前
記セラミツク基板上を封止する樹脂とを有するこ
とを特徴とする半導体装置。 A ceramic substrate having a plurality of conductor patterns and a cavity opened on the surface, a semiconductor chip mounted on the conductor pattern on the ceramic substrate, an electrode of the semiconductor chip and another ceramic substrate on the ceramic substrate. 1. A semiconductor device comprising: a thin metal wire that connects the semiconductor chip to a conductor pattern; and a resin that covers the semiconductor chip and the thin metal wire and seals the ceramic substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2262289U JPH02113338U (en) | 1989-02-27 | 1989-02-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2262289U JPH02113338U (en) | 1989-02-27 | 1989-02-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02113338U true JPH02113338U (en) | 1990-09-11 |
Family
ID=31240899
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2262289U Pending JPH02113338U (en) | 1989-02-27 | 1989-02-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02113338U (en) |
-
1989
- 1989-02-27 JP JP2262289U patent/JPH02113338U/ja active Pending