JPH02113438U - - Google Patents
Info
- Publication number
- JPH02113438U JPH02113438U JP2261689U JP2261689U JPH02113438U JP H02113438 U JPH02113438 U JP H02113438U JP 2261689 U JP2261689 U JP 2261689U JP 2261689 U JP2261689 U JP 2261689U JP H02113438 U JPH02113438 U JP H02113438U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor integrated
- integrated circuit
- mos transistor
- transistor
- bipolar transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Electronic Switches (AREA)
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図は第１図に示す半導体集積回路の詳細を示
す回路図、第３図は本考案の一使用例を示す回路
図、第４図従来の一例を示す回路図である。
１０……ＰｃｈＭＯＳトランジスタ、１１，１
２……ＮｃｈＭＯＳトランジスタ、４０……抵抗
、５０……入力信号、５１……論理出力信号、５
２……負荷駆動出力信号、６０……ＣＭＯＳイン
バータ回路、６１……バイポーラ出力回路、７０
……インバータ、７１，７２……トランスフアゲ
ート、８０，８１……出力段インバータ、９０，
９１……外部出力。
FIG. 1 is a block diagram showing an embodiment of the present invention.
2 is a circuit diagram showing details of the semiconductor integrated circuit shown in FIG. 1, FIG. 3 is a circuit diagram showing an example of the use of the present invention, and FIG. 4 is a circuit diagram showing an example of the prior art. 10...PchMOS transistor, 11,1
2...NchMOS transistor, 40...Resistor, 50...Input signal, 51...Logic output signal, 5
2...Load drive output signal, 60...CMOS inverter circuit, 61...Bipolar output circuit, 70
... Inverter, 71, 72 ... Transfer gate, 80, 81 ... Output stage inverter, 90,
91...External output.
Claims (1)
とを複合して用いる半導体集積回路において、負
荷を駆動する前記バイポーラトランジスタの動作
を制御するための前記ＭＯＳトランジスタをＣＭ
ＯＳ論理回路として併用することを特徴とする半
導体集積回路。 In a semiconductor integrated circuit using a bipolar transistor and a MOS transistor in combination, the MOS transistor for controlling the operation of the bipolar transistor that drives a load is CM.
A semiconductor integrated circuit characterized in that it is also used as an OS logic circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2261689U JPH02113438U (en) | 1989-02-27 | 1989-02-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2261689U JPH02113438U (en) | 1989-02-27 | 1989-02-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02113438U true JPH02113438U (en) | 1990-09-11 |
Family
ID=31240888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2261689U Pending JPH02113438U (en) | 1989-02-27 | 1989-02-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02113438U (en) |
-
1989
- 1989-02-27 JP JP2261689U patent/JPH02113438U/ja active Pending