JPH02114932U - - Google Patents

Info

Publication number
JPH02114932U
JPH02114932U JP1989022308U JP2230889U JPH02114932U JP H02114932 U JPH02114932 U JP H02114932U JP 1989022308 U JP1989022308 U JP 1989022308U JP 2230889 U JP2230889 U JP 2230889U JP H02114932 U JPH02114932 U JP H02114932U
Authority
JP
Japan
Prior art keywords
chip component
wiring board
electrodes
electrode
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989022308U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989022308U priority Critical patent/JPH02114932U/ja
Publication of JPH02114932U publication Critical patent/JPH02114932U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes

Landscapes

  • Wire Bonding (AREA)
  • Credit Cards Or The Like (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案による配線基板を用いた情報カ
ードの一実施例を示す略線的側面図、第2図はチ
ツプ部品の電極及びバンプの接合状態を示す略線
図、第3図は従来の情報カード読取システムの構
成を示す略線図、第4図はその情報カードの電気
的構成を示す略線的ブロツク図、第5図は従来の
配線基板を示す略線的側面図、第6図は問題点の
説明に供する略線的側面図である。 4,30……情報カード、4A……基板、4E
……配線パターン、15……チツプ部品、16…
…電極、17,18……バンプ、21,31……
配線基板。
Fig. 1 is a schematic side view showing an embodiment of an information card using a wiring board according to the present invention, Fig. 2 is a schematic diagram showing the bonding state of electrodes and bumps of chip components, and Fig. 3 is a conventional diagram. FIG. 4 is a schematic block diagram showing the electrical configuration of the information card; FIG. 5 is a schematic side view showing a conventional wiring board; FIG. The figure is a schematic side view for explaining the problem. 4, 30... Information card, 4A... Board, 4E
...Wiring pattern, 15...Chip parts, 16...
...Electrode, 17,18...Bump, 21,31...
wiring board.

Claims (1)

【実用新案登録請求の範囲】 チツプ部品の表面に形成した複数の電極をそれ
ぞれ対応する接合部材によつて当該電極に対向す
る配線パターンに接合するようになされた配線基
板において、 上記チツプ部品の表面の上記電極の形成位置を
、上記チツプ部品の側端面から上記接合部材の平
面形状の大きさと同等又はそれ以上の長さ分だけ
内側に形成した ことを特徴とする配線基板。
[Claims for Utility Model Registration] In a wiring board in which a plurality of electrodes formed on the surface of a chip component are bonded to wiring patterns facing the electrodes by respective bonding members, the surface of the chip component The wiring board is characterized in that the electrode is formed inward from the side end surface of the chip component by a length equal to or greater than the planar size of the bonding member.
JP1989022308U 1989-02-28 1989-02-28 Pending JPH02114932U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989022308U JPH02114932U (en) 1989-02-28 1989-02-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989022308U JPH02114932U (en) 1989-02-28 1989-02-28

Publications (1)

Publication Number Publication Date
JPH02114932U true JPH02114932U (en) 1990-09-14

Family

ID=31240303

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989022308U Pending JPH02114932U (en) 1989-02-28 1989-02-28

Country Status (1)

Country Link
JP (1) JPH02114932U (en)

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