JPH0348230U - - Google Patents

Info

Publication number
JPH0348230U
JPH0348230U JP1989108462U JP10846289U JPH0348230U JP H0348230 U JPH0348230 U JP H0348230U JP 1989108462 U JP1989108462 U JP 1989108462U JP 10846289 U JP10846289 U JP 10846289U JP H0348230 U JPH0348230 U JP H0348230U
Authority
JP
Japan
Prior art keywords
bonding
wire
rows
electrode terminals
staggered pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989108462U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989108462U priority Critical patent/JPH0348230U/ja
Publication of JPH0348230U publication Critical patent/JPH0348230U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案による電子部品のワイヤボンデ
イング構造の一実施例を示す概略平面図である。
第２図は従来のワイヤボンデイング構造の一例を
示す概略平面図、第３図は第２図のワイヤボンデ
イング部の部分断面図である。 １１……電子部品、１２……電極端子、１３…
…チツプ、１４，１４ａ，１４ｂ，１４ｃ……ワ
イヤボンデイングパツド、１５……ボンデイング
ワイヤ、１６……ボンデイングパツドの端部。 FIG. 1 is a schematic plan view showing an embodiment of a wire bonding structure for electronic components according to the present invention.
FIG. 2 is a schematic plan view showing an example of a conventional wire bonding structure, and FIG. 3 is a partial sectional view of the wire bonding part in FIG. 2. 11...Electronic component, 12...Electrode terminal, 13...
...chip, 14, 14a, 14b, 14c... wire bonding pad, 15... bonding wire, 16... end of bonding pad.

Claims (1)

【実用新案登録請求の範囲】 電子部品の側縁に沿つて千鳥格子状をなして二
列に設けられた複数の電極端子と、これに対応す
る複数のボンデイングパツドとをボンデイングワ
イヤによりワイヤボンデイングする構造において
、 上記複数のボンデイングパツドが電極端子に対
応して千鳥格子状をなして二列に配置され且つ各
ボンデイングパツドがボンデイングワイヤの延び
る方向に沿つて設けられていることを特徴とする
、電子部品のワイヤボンデイング構造。[Claims for Utility Model Registration] A plurality of electrode terminals provided in two rows in a staggered pattern along the side edge of an electronic component and a plurality of corresponding bonding pads are connected by bonding wire. In the bonding structure, the plurality of bonding pads are arranged in two rows in a staggered pattern corresponding to the electrode terminals, and each bonding pad is provided along the direction in which the bonding wire extends. Features a wire bonding structure for electronic components.
JP1989108462U 1989-09-16 1989-09-16 Pending JPH0348230U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989108462U JPH0348230U (en) 1989-09-16 1989-09-16

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989108462U JPH0348230U (en) 1989-09-16 1989-09-16

Publications (1)

Publication Number Publication Date
JPH0348230U true JPH0348230U (en) 1991-05-08

Family

ID=31657103

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989108462U Pending JPH0348230U (en) 1989-09-16 1989-09-16

Country Status (1)

Country Link
JP (1) JPH0348230U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005167004A (en) * 2003-12-03 2005-06-23 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51109774A (en) * 1975-03-20 1976-09-28 Nippon Electric Co
JPS5779629A (en) * 1980-11-06 1982-05-18 Nec Corp Integrated circuit device
JPS59107551A (en) * 1982-12-13 1984-06-21 Hitachi Ltd Semiconductor device
JPS6055648A (en) * 1983-09-07 1985-03-30 Toshiba Corp High density mounting substrate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51109774A (en) * 1975-03-20 1976-09-28 Nippon Electric Co
JPS5779629A (en) * 1980-11-06 1982-05-18 Nec Corp Integrated circuit device
JPS59107551A (en) * 1982-12-13 1984-06-21 Hitachi Ltd Semiconductor device
JPS6055648A (en) * 1983-09-07 1985-03-30 Toshiba Corp High density mounting substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005167004A (en) * 2003-12-03 2005-06-23 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method thereof

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