JPH0211547U - - Google Patents

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Publication number
JPH0211547U
JPH0211547U JP8620588U JP8620588U JPH0211547U JP H0211547 U JPH0211547 U JP H0211547U JP 8620588 U JP8620588 U JP 8620588U JP 8620588 U JP8620588 U JP 8620588U JP H0211547 U JPH0211547 U JP H0211547U
Authority
JP
Japan
Prior art keywords
digital input
outputting
outputs
input means
sampling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8620588U
Other languages
Japanese (ja)
Other versions
JPH073499Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8620588U priority Critical patent/JPH073499Y2/en
Publication of JPH0211547U publication Critical patent/JPH0211547U/ja
Application granted granted Critical
Publication of JPH073499Y2 publication Critical patent/JPH073499Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Signal Processing For Digital Recording And Reproducing (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の1つの実施例に係るDAT
の構成を示すブロツク図、第2図は第1図中のマ
イクロコンピユータの動作を示すフローチヤート
である。 10:デジタルI/O、12:信号処理回路、
14:マイクロコンピユータ、16:操作部、1
8:表示部、20:セレクタ回路、22:周波数
比較回路。
Figure 1 shows a DAT according to one embodiment of this invention.
FIG. 2 is a flowchart showing the operation of the microcomputer shown in FIG. 10: Digital I/O, 12: Signal processing circuit,
14: Microcomputer, 16: Operation unit, 1
8: Display section, 20: Selector circuit, 22: Frequency comparison circuit.

Claims (1)

【実用新案登録請求の範囲】 (1) デジタル入力から同期をとりながらデジタ
ルサンプリングデータ、クロツク、サブコードを
抽出し、かつ、非同期時には非同期検知信号を出
力するデジタル入力手段と、 異なるサンプリング周波数クロツクを発生する
複数のクロツク発生手段と、 選択手段の出力クロツクとデジタル入力手段の
抽出したクロツクとの周波数比較を行い、一致し
たとき一致信号を出力する周波数比較手段と、 この周波数比較手段が一致信号を出力していな
いとき、一致信号を出力するまで選択手段の切り
換え制御を行う切り換え制御手段と、 デジタル入力手段が非同期検知信号を出力して
いないときは周波数比較手段が一致信号を出力し
ているときの選択手段の選択位置に係るサンプリ
ング周波数データを出力し、デジタル入力手段が
非同期検知信号を出力した直後はデジタル入力手
段の抽出したサブコードに含まれるサンプリング
周波数データを出力するサンプリング周波数出力
手段と、 を備えたことを特徴とするDAT。 (2) デジタル入力から同期をとりながらデジタ
ルサンプリングデータ、クロツク、サブコードを
抽出し、かつ、非同期時には非同期検知信号を出
力するデジタル入力手段と、 異なるサンプリング周波数クロツクを発生する
複数のクロツク発生手段と、 選択手段の出力クロツクとデジタル入力手段の
抽出したクロツクとの周波数比較を行い、一致し
たとき一致信号を出力する周波数比較手段と、 この周波数比較手段が一致信号を出力していな
いとき、一致信号を出力するまで選択手段の切り
換え制御を行う切り換え制御手段と、 周波数比較手段が一致信号を出力しているとき
の選択手段の選択位置に係るサンプリング周波数
データを出力するサンプリング周波数出力手段と
、 を設け、 前記切り換え制御手段は、デジタル入力手段が
非同期検知信号を出力した直後はデジタル入力手
段の抽出したサブコードに含まれるサンプリング
周波数データが示す位置に選択手段を切り換える
ようにしたこと、 を特徴とするDAT。
[Claims for Utility Model Registration] (1) Digital input means that extracts digital sampling data, clocks, and subcodes while being synchronized from digital inputs, and outputs an asynchronous detection signal when they are out of synchronization, and clocks with different sampling frequencies. a plurality of clock generation means, a frequency comparison means for comparing the frequencies of the output clock of the selection means and the clock extracted by the digital input means, and outputting a coincidence signal when they match; When the digital input means is not outputting an asynchronous detection signal, the frequency comparison means is outputting a coincidence signal.When the digital input means is not outputting an asynchronous detection signal, the frequency comparison means is outputting a coincidence signal. sampling frequency output means that outputs sampling frequency data related to the selected position of the selection means, and immediately after the digital input means outputs the asynchronous detection signal, outputs the sampling frequency data included in the subcode extracted by the digital input means; DAT is characterized by being equipped with. (2) A digital input means that extracts digital sampling data, a clock, and a subcode while maintaining synchronization from the digital input, and outputs an asynchronous detection signal when the clocks are out of synchronization, and a plurality of clock generation means that generate clocks with different sampling frequencies. , frequency comparison means for comparing the frequencies of the output clock of the selection means and the clock extracted by the digital input means and outputting a coincidence signal when they match; and a frequency comparison means for outputting a coincidence signal when the frequency comparison means does not output a coincidence signal; switching control means for controlling switching of the selection means until the frequency comparison means outputs a matching signal; and sampling frequency output means for outputting sampling frequency data related to the selected position of the selection means when the frequency comparison means outputs a coincidence signal. Immediately after the digital input means outputs the asynchronous detection signal, the switching control means switches the selection means to the position indicated by the sampling frequency data included in the subcode extracted by the digital input means. D.A.T.
JP8620588U 1988-06-29 1988-06-29 DAT Expired - Lifetime JPH073499Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8620588U JPH073499Y2 (en) 1988-06-29 1988-06-29 DAT

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8620588U JPH073499Y2 (en) 1988-06-29 1988-06-29 DAT

Publications (2)

Publication Number Publication Date
JPH0211547U true JPH0211547U (en) 1990-01-24
JPH073499Y2 JPH073499Y2 (en) 1995-01-30

Family

ID=31310848

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8620588U Expired - Lifetime JPH073499Y2 (en) 1988-06-29 1988-06-29 DAT

Country Status (1)

Country Link
JP (1) JPH073499Y2 (en)

Also Published As

Publication number Publication date
JPH073499Y2 (en) 1995-01-30

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