JPH02115938A - Microprogram error detection circuit - Google Patents

Abstract

PURPOSE:To detect the fault of a microprogram readout register without generating instruction time out by informing a correctable error detected again in a microprogram in which the correctable error is corrected as an incorrectable error. CONSTITUTION:The microprogram and an ECC(error correct code) bit read out from a control memory device 1 are stored in the readout register 3 via a selector 2, and ECC check is applied by an error detection circuit 4. When a 1-bit error is detected, a correctable error detection FF 6 is set, and also, it is corrected at an error correction circuit 5, and the ECC check is applied again by the error detection circuit 4. At this time, when the 1-bit error is detected by the ECC check, a register error registration FF 7 is set, and the 1-bit error is registered as an incorrectable hardware error.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram error detection circuit, and in particular to an error detection and correction method in a microprogram control device for microprogram control. When a correctable error is detected in the microprogram read and held in the microprogram read register, the correctable error in the microprogram is always corrected.

In such a conventional microprogram controller, −
If a correctable error is detected again after the error has been corrected, the correctable error will be corrected. The disadvantage of this method is that correction operations for the correctable errors are performed continuously, resulting in an instruction timeout.

The present invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it is possible to eliminate the failure of the microprogram read register without causing an instruction timeout when the failure occurs in the microprogram read register. The present invention aims to provide a microprogram error detection circuit that can detect microprogram errors.

A microprogram error detection circuit according to the present invention includes: a register for holding microprograms successively retrieved from a control memory; error detection means for detecting a correctable error in the microprogram held in the register;
a microprogram error detection circuit comprising: error correction means for correcting the correctable error and storing it in the register; The present invention is characterized in that, when the correctable error is detected by the error detection means in the held microprogram, means is provided for notifying the correctable error of the microprogram as an uncorrectable error.

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 4, a control storage device 1 includes a microprogram and an error correctable ECC (error correcting code).

de) bits are stored in this control storage device 1.
The microprogram and ECC bits read from the signal line 101 are sent to the microprogram read register (hereinafter referred to as the read register) via the selector 2.
3.

Cell/actor 2 is read from control memory 1 and signal line 1
Microprogram and EC input via 01
One of the C bit and the microprogram and ECC bit input via the signal line 105 after a 1-bit error has been corrected by the error correction circuit 5 is selected according to the signal from the error detection circuit 4, and the signal ffl is selected. 102 to the read register 3.

That is, when the error detection circuit 4 detects a 1-bit error, the microprogram and ECC bit from the error correction circuit 5 are selected, and when the error detection circuit 4 does not detect an error, the control memory/1 bit error is selected.
The original microprogram and ECC bits are selected.

The microprogram and ECC bits stored in read register 3 are sent to error detection circuit 4 and error correction circuit 5 via signal line 103.

The error detection circuit 4 detects 1-bit errors and 2-bit errors in the microprogram and ECC bits sent from the read register 3, and sends the detection results to the selector 2 and the correctable error detection flip-flop ( It is sent to the read register error registration FF (hereinafter referred to as register error registration FF) 7 via the signal line 107.

The error correction circuit 5 corrects a 1-set error in the microprogram and ECC bit sent from the read register 3, and the corrected microprogram and ECC bit are sent to the selector 2 via the signal line 105.

Correctable error detection PF 6 is set when the error detection circuit 4 detects a 1-set error, and outputs its contents to the error detection circuit 4 via the signal line 106 .

Register error registration FF7 is correctable error detection FF6
It is set when a 1-bit error is detected in the error detection circuit 4 when the 1-bit error is set, and even though the 1-bit error has been corrected, a 1-bit error has occurred again. Registered as an error.

FIG. 2 is a time chart showing the operation of one embodiment of the present invention. The operation of an embodiment of the present invention will be explained using FIG. 1 and FIG. 2.

The microprogram and ECC bits read from control storage device 1 at timing T1 are stored in read register 3 via selector 2 at timing T2.

The microprogram and ECC bits stored in the read register 3 are immediately converted to ECC by the error detection circuit 4.
A check is performed.

When a 1-set error is detected by this ECC check, the signal line 1 from the error detection circuit 4 is output at timing T3.
The signal on 04 becomes active, the correctable error detection FF6 is set, and the microprogram and ECC bits corrected by the error correction circuit 5 are stored in the read register 3 via the selector 2.

The microprogram and ECC bits stored in this read register 3 are again checked by the error detection circuit 4.
A C check is performed.

At this time, if a 1-set error is detected by the ECC check, since the correctable error detection FF6 is set, the signal from the error detection circuit 4 is output at timing T4! The signal on 1107 becomes active, register error register 81 F F 7 is set, and this 1
The error is registered as an uncorrectable hardware error.

By setting register error registration FF7,
This hardware error is notified to a high-level device or a diagnostic device (not shown), and the high-level device or diagnostic device performs failure processing.

Therefore, if the read register 3 is out of order and a 1-set error is detected again in the microprogram and ECC bits that have been corrected by the error correction circuit 5, this correctable error turns into an uncorrectable hardware error. Since the failure of the read register 3 can be detected without causing an instruction timeout, the host device or diagnostic device is notified as follows.

In this way, the error correction port F! ? When the error detection circuit 4 detects a correctable error again in the microprogram and ECC bit in which the correctable error was corrected in step 15, the correctable error is registered in the register error registration FF7 as an uncorrectable error. By notifying a host device or a diagnostic device, even if a failure occurs in the read register 3 instead of a failure in the control storage device 1, the failure in the read register 3 can be detected without causing an instruction timeout. Can be done.

As explained above, according to the present invention, a correctable error is detected in a microprogram read from a control memory and held in a microprogram read register, and a correctable error is detected in a microprogram read from a control memory and held in a microprogram read register. When a correctable error is detected in the program again, the correctable error in the microprogram is notified as an uncorrectable error, thereby preventing an instruction timeout even if a failure occurs in the microprogram read register. This has the advantage that failures in microprogram successive registers can be detected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a time chart showing the operation of the embodiment of the invention. Explanation of symbols of main parts 1...Control storage device 3...Microprogram read register 4.
...Error detection circuit 5 ...Error correction circuit 6 ...Correctable error detection flip-flop 7
・・・・・・Read register error registration flip-flop

Claims (1)

[Claims] (1) a register for holding a microprogram read from a control memory; an error detection means for detecting a correctable error in the microprogram held in the register; a microprogram error detection circuit comprising an error correction means for storing in the register, the correctable error being corrected by the error correction means;
A microprogram, characterized in that, when the correctable error is detected by the error detection means in the microprogram held in the register, means is provided for notifying a correctable error in the microprogram as an uncorrectable error. Error detection circuit.