JPH0211599U - - Google Patents
Info
- Publication number
- JPH0211599U JPH0211599U JP8565188U JP8565188U JPH0211599U JP H0211599 U JPH0211599 U JP H0211599U JP 8565188 U JP8565188 U JP 8565188U JP 8565188 U JP8565188 U JP 8565188U JP H0211599 U JPH0211599 U JP H0211599U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- shift register
- semiconductor integrated
- data input
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 230000003068 static effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Manipulation Of Pulses (AREA)
- Pulse Circuits (AREA)
Description
第１図は本考案の１実施例である半導体集積回
路（ＭＯＳ型スタテイツク・シフトレジスタ回路
）のブロツク図、第２図は第１図における各部の
波形図、第３図は従来の半導体集積回路（ＭＯＳ
型スタテイツク・シフトレジスタ回路）のブロツ
ク図、第４図及び第５図は第３図の各部波形図で
あり、第４図は信号の遅延を無視した理想的状態
の波形図、第５図は遅延を考慮した場合の波形図
である。
１―１，１―２，１―３……シフトレジスタユ
ニツト、２……データ入力信号駆動素子、３……
クロツク入力信号駆動素子、４……データ入力端
子、５……クロツク入力端子、６……浮遊容量（
容量性負荷）、７……遅延回路。
Figure 1 is a block diagram of a semiconductor integrated circuit (MOS type static shift register circuit) which is an embodiment of the present invention, Figure 2 is a waveform diagram of each part in Figure 1, and Figure 3 is a conventional semiconductor integrated circuit. (MOS
Figures 4 and 5 are waveform diagrams of each part of Figure 3, Figure 4 is a waveform diagram of the ideal state ignoring signal delay, and Figure 5 is a block diagram of the static shift register circuit. FIG. 4 is a waveform diagram when delay is taken into account. 1-1, 1-2, 1-3...Shift register unit, 2...Data input signal driving element, 3...
Clock input signal driving element, 4...data input terminal, 5...clock input terminal, 6...stray capacitance (
capacitive load), 7...Delay circuit.
Claims (1)
おいて、データ入力の前段に遅延回路を設けたこ
とを特徴とする半導体集積回路。 A semiconductor integrated circuit characterized in that a MOS static shift register circuit is provided with a delay circuit at a stage before data input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8565188U JPH0211599U (en) | 1988-06-28 | 1988-06-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8565188U JPH0211599U (en) | 1988-06-28 | 1988-06-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0211599U true JPH0211599U (en) | 1990-01-24 |
Family
ID=31310304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8565188U Pending JPH0211599U (en) | 1988-06-28 | 1988-06-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0211599U (en) |
-
1988
- 1988-06-28 JP JP8565188U patent/JPH0211599U/ja active Pending
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