JPH02116097A - shift register - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a static type shift register used for circuit configuration of semiconductor integrated circuits.

2. Description of the Related Art Shift registers used in CMO8 semiconductor integrated circuits are classified into dynamic types and static types based on their storage methods. Dinah Mink types usually have a memory time of 2~
Since it is short, less than 5m5ec, it is necessary to continue shifting within this time.

Therefore, the shift downtime is 2 to 5 msec.
The static type is not used in applications where there is more than that and it is desired to store data before the pause, or where the lower limit frequency of shift is 100 to 300 Hz or less.

Conventionally, one bit of this static type is configured as shown in FIG. That is, the output of transmission gate 1 into which data D is input is connected to the input of inverter 5 and the output of transmission gate 2, the output of inverter 5 is connected to the input of inverter 6 and the input of transmission gate 3, and the output of inverter 6 is connected to the input of inverter 6 and the input of transmission gate 3. The output of is connected to the input of transmission gate 2. The output of transmission gate 3 is connected to the input of inverter and transmission gate 4.
The output of the inverter is connected to the output of the inverter 8.
The output of the inverter 8 is connected to the input of the transmission gate 4. The synchronization signal C and its inverted signal C are input to the transmission gates 1.2 and 3.4, and when the synchronization signal C is at "H" level, the transmission gates 2 and 3 are conductive, and the transmission gate 1.4 is cut off. When the synchronizing signal C is at the "LI+" level, the opposite state occurs, and shift data is output from the data output Q of the inverter.

FIG. 5 shows the timing chart of FIG.

When the synchronizing signal C is at the "L" level, the input a of the inverter 5 becomes "L" due to the data D passing through the transmission gate 1.
The output of the inverter 5 and the input b of the inverter 6 are "itH", and the output C of the inverter 6 is "L $1. At this time, the transmission gate 3 receives the synchronization signal C is “L”, so it is in a cutoff state,
The latch formed by the inverter 7.8 and the transmission gate 4 stores the data immediately before the data D and outputs it from the data output Q. Subsequently, when the synchronization signal C becomes "H", the transmission gate 1 is cut off, and the inverter and
Data is stored in a latch composed of a transmission gate 6 and a transmission gate 2. At this time, since the transmission gate 4 is cut off, the input d of the inverter becomes "H", the same as b, through the transmission gate 3, and is inverted and outputted by the inverter 7, and the data output Q becomes It L 11. This makes the data output Q equal to the data output. Further, the output e of the inverter 8 is set to "jlH" by the data output Q, and then when the synchronization signal C becomes "L", the data is stored by the latch formed by the inverter 7.8 and the transmission gate 4, and the data is output. Q continues to output It L It. At this time, in the latch formed by inverters 5 and 6 and transmission gate 2, transmission gate 2 is cut off, and b is input from II HII of data D through transmission gate 1.
Luc becomes it Hu and takes in data D.

A static type shift register is constructed by connecting such 1-bit shift registers in series.

Problems to be Solved by the Invention In such a conventional configuration, a total of eight elements, including four transmission gate elements and four inverter elements, are required to configure one bit of the shift register. For this reason, semiconductor integrated circuits used in applications that require static shift registers with a large number of bits and high voltage drive require high breakdown voltage, so the high breakdown voltage section and the logic section are subject to the same masking rule. We are trying to achieve high integration by creating a new design or by reducing the mask rule only for the logic part. However, the former requires a large chip area, while the latter increases the number of process steps and reduces yield.

Chip costs for both have increased.

SUMMARY OF THE INVENTION An object of the present invention is to provide a shift register that can reduce the number of elements necessary to construct a 1-bit shift register.

Means for Solving the Problems The shift register of the present invention connects the output of a transmission gate into which data is input to the input of a first clocked inverter, and connects the output of the first clocked inverter to the input of the inverter. A second clocked inverter is interposed between the input and output of the inverter, and a synchronizing signal is applied to the transmission gate and the first and second clocked inverters to connect the transmission gate and the second clocked inverter. A first state in which the second clocked inverter is in the on state and the first clocked inverter is in the off state, and a second state in which the transmission gate and the second clocked inverter are in the off state and the first clocked inverter is in the off state. The inverter is characterized in that the inverter is switched to a second state of being on, and shift data is obtained from the output of the inverter.

According to this configuration, the first clocked inverter is interposed between the input of the latch circuit composed of the inverter and the second clocked inverter and the transmission gate,
The data held in the parasitic capacitance on the input side of the first clocked inverter in the first state is transmitted to the subsequent stage in the second state, thereby shifting the data input to the transmission gate.

EXAMPLE Hereinafter, an example of the present invention will be described based on FIGS. 1 to 3.

FIG. 1 shows the shift register of the present invention, transmission gate 9.
is used as an input terminal for data D, the other side of the transmission gate 9 is connected to the input of the first clocked inverter 10, the output of the first clocked inverter 10 is connected to the input of the inverter 11, The output of inverter 11 is
The output of the second clocked inverter 12 is connected to the input of the inverter 11.

The output of the inverter 11 is the data output Q.

The synchronizing signal C and its inverted signal C are input to the transmission gate 9 and the first and second clocked inverters 10 and 12. Here, 13 and 14 are the resistance components of the output leakage of the transmission gate 9, and 15 is the parasitic capacitance such as the gate capacitance of the first clocked inverter 10.

FIG. 2 is a timing chart of FIG. 1, where a is the input signal of the first clocked inverter lO, and b is the input signal of the first
, the output signal of the second clocked inverter 10°12. When the synchronization signal C is “L”, the transmission gate 9
Through this, the input signal a of the first clocked inverter 10 is set to "L" due to the "L" level of data D. At this time, the first clocked inverter IO is in a state where the input/output relationship is separated (off state) due to the synchronization signal C, and the second clocked inverter IO is in an inverting state (on state) due to the inverter 11 and the synchronization signal C. - The data immediately before data D is stored in the latch formed by the inverter 12.

When the synchronization signal C becomes "H11", the transmission gate 9 is cut off, and the input signal a of the first clocked inverter 10 is separated from the data D, but is kept at L level by the parasitic capacitance 15. do.

Here, the parasitic capacitance 15 has begun to be charged by the output leakage resistor 13.14. At this time, the first clocked
Inverter IO is brought into an inverting state by synchronization signal C, and second clocked inverter 12 is turned off, so that the output signal S becomes H0. Output signal
By going high, the inverter 11 inverts and outputs the output data Q, which becomes tz L n. This state continues stably while the potential level of the input signal a is 11 L 11. This stable state is due to output leakage. Determined by the charging time of the parasitic capacitance 15 by the resistor 13.14, typically 2-5 m5
It is within ec.

Here, the synchronization signal C becomes L within 2 to 5 msec.
'', the second clocked inverter 12 enters the inverting operation state, forms a latch with the inverter 11, and can store ``LII''. At this time, the first clocked inverter 10 is in the off state, and 41 HII of data D is taken in through the transmission gate 9.
Set input signal a to "H".

As mentioned above, the period of 'H'' is 2 to 5 msec
If the synchronization signal C is as shown below, the II L" period of the synchronization signal C is structured to be stored by a latch, so it can function in the same way as a static shift register. In other words, it can function as a shift pause period. is 2~5 m s e
In applications where there is more than C and it is desired to store the data before the pause, the synchronization signal C may be paused at "L'", and the lower limit frequency of the shift is 100 to 30.
Even in applications where the frequency is below 0Hz, the “H” of the synchronization signal C can be set to 2.
It can be used by keeping it below 5m5ec.

If it is difficult to provide such a synchronization signal C from the outside, as shown in FIG. By providing a simple control circuit configured to input the inverted signal of the clock signal CK signal through an odd number of inverters 16 to the other input, take a NAND product, and pass the clock signal G through the inverter 18,
Using the rising edge of K, it is possible to create a short synchronization signal C of H'''.

With this configuration, the shift register has the configuration of the transmission gate 9 and the first . Second clocked inverter 10.
12 and Inverter II, a total of 4 elements, compared to 8 elements for 1 bit in a conventional static type shift register.
Compared to the number of elements required, the same function can be achieved with half the number of elements. Note that the number of components of the control circuit is an odd number (usually 3 to 7) of inverters 16 and NA
A total of 5 to 9 elements of the ND gate 17 and the inverter 18 are required, which is a small number of elements, and this shows that in a shift register of 3 bits or more, the number of elements can be reduced compared to a conventional shift register even if a control circuit is provided.

Effects of the Invention As described above, according to the present invention, one bit of a shift register is configured with a total of four elements, one transmission gate element, two clocked inverters, and one inverter element, by actively using parasitic capacitance. Therefore, the number of elements can be reduced to 1/2 compared to the 8 elements required for the configuration of a conventional static type shift register. Therefore, if created using the same mask rule, a shift register with the same number of bits can be constructed with half the chip area compared to the conventional one.
It is possible to significantly reduce chip cost.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of a shift register of the present invention,
Figure 2 is a time chart of the main parts of the shift register, Figure 3 is a configuration diagram of a control circuit that creates a synchronization signal used in the shift register from a clock signal, and Figure 4 is a configuration diagram of a conventional shift register. FIG. 5 is a time chart of the main parts of the shift register. 9... Transmission gate, lQ... First clocked inverter, 11... Inverter, 12... Second clocked inverter, 15... Parasitic capacitance, C2C
...Synchronization signal, D...data, Q...data output. Agent Yoshihiro Morimoto Figure 1 Figure 4 @ Figure 2 Figure 5 Figure 3

Claims (1)

[Claims] 1. Connect the output of the transmission gate into which data is input to the input of the first clocked inverter, connect the output of the first clocked inverter to the input of the inverter, and connect the input and output of the inverter. A second clocked inverter is interposed in the clocked inverter, and a synchronizing signal is applied to the transmission gate and the first and second clocked inverters so that when the transmission gate and the second clocked inverter are on, the first clocked inverter is in the on state. a first state in which the clocked inverter is in an off state; and a second state in which the transmission gate and the second clocked inverter are in an off state and the first clocked inverter is in an on state; A shift register that obtains shift data from the output of the inverter.