JPH02116152A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH02116152A JPH02116152A JP26969488A JP26969488A JPH02116152A JP H02116152 A JPH02116152 A JP H02116152A JP 26969488 A JP26969488 A JP 26969488A JP 26969488 A JP26969488 A JP 26969488A JP H02116152 A JPH02116152 A JP H02116152A
- Authority
- JP
- Japan
- Prior art keywords
- board
- wiring
- chips
- integrated circuit
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims description 5
- 238000001721 transfer moulding Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 3
- 229910000679 solder Inorganic materials 0.000 abstract description 3
- 239000003990 capacitor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000010409 thin film Substances 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は混成４Ａ積回路装置に関し、特に、実装密度の
大きなトランスファーモールド型の混成集積回路装置に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid 4A integrated circuit device, and particularly to a transfer mold type hybrid integrated circuit device with a high packaging density.
従来、この種の混成集積回路装置としては、第３図（ａ
）、（ｂ）に示すように、リードフレーム３１に貼り付
けられたプリント配線基板３３上に、各種ＩＣチップ及
びシリコンウェハ上に薄膜パターンを形成して作成した
受動素子チップ等の搭載チップ３５を搭載した後、ボン
ディングワイヤ３４により、リードフレーム３１とプリ
ント配線基板３３間及び搭載チップ３５間に電気的な接
続を施し、トランスファーモールド樹脂３７にて封止し
た構造となっていた。Conventionally, this type of hybrid integrated circuit device is shown in Fig. 3 (a).
), (b), on a printed wiring board 33 attached to a lead frame 31, mounting chips 35 such as various IC chips and passive element chips made by forming thin film patterns on silicon wafers are mounted. After mounting, electrical connections were made between the lead frame 31 and the printed wiring board 33 and between the mounted chip 35 using bonding wires 34, and the structure was sealed with a transfer mold resin 37.
しかしながら、上述した従来の混成集積回路装置は、配
線基板としてプリント配線基板を用いている為、例えば
、シリコン基板等と比較して、その平坦度や適用可能な
プロセスの差異から、パターンの微細化が難しく、一般
的には、数十ミクロン程度までの加工が限界であるとい
う欠点がある。However, since the above-mentioned conventional hybrid integrated circuit device uses a printed wiring board as a wiring board, for example, compared to a silicon substrate, the pattern can be finer due to differences in its flatness and applicable processes. The drawback is that processing is generally limited to a few tens of microns.
又、搭載ＩＣチップがボンディングワイヤにより接続さ
れる為、配線基板側のランドパターンも大きなものとな
り、配線を引き回す上で大きな障害となるという欠点も
ある。Furthermore, since the mounted IC chips are connected by bonding wires, the land pattern on the wiring board side becomes large, which also has the disadvantage of becoming a major obstacle in routing the wiring.
さらに、抵抗、コンデンサ等の受動素子は、回路上必要
な個数及び種類を１個又は数個のチップに集中して作り
込む為、受動素子チップまでの配線の引き回しが多くな
り、配線パターンに関する設計上の困難さはさらに大き
なものとなるという欠点もある。Furthermore, since the number and types of passive elements such as resistors and capacitors required for the circuit are concentrated on one or a few chips, there is a need for many wiring routes to the passive element chips, and the design of wiring patterns The drawback is that the above difficulties are even greater.
本発明の目的は、パターンの微細化が可能で、配線の引
き回わしが少く、配線パターンの設計が容易な混成集積
回路装置を提供することにある。An object of the present invention is to provide a hybrid integrated circuit device that allows finer patterns, requires less wiring, and facilitates the design of wiring patterns.
本発明は、配線基板上に複数のＩＣチップを搭載し、ト
ランスファーモールドして成る混成集積回路装置に於い
て、前記配線基板としてシリコン基板を使用し、且つ、
フリップチップをバンプ接続した部分を有している。The present invention provides a hybrid integrated circuit device in which a plurality of IC chips are mounted on a wiring board and transfer molded, in which a silicon substrate is used as the wiring board, and
It has a part where flip chips are bump-connected.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）、（ｂ）は本発明の第１の実施例の平面図
及び断面図である。FIGS. 1(a) and 1(b) are a plan view and a sectional view of a first embodiment of the present invention.
第１の実施例は、第１図（ａ）、（ｂ）に示すように、
リードフレーム１１の基板搭載用マウントアイランド１
２に貼り付けられた数ミクロン幅の微細パターンにより
構成されるシリコン配線基板１３上に各種ＩＣチップ等
の搭載チップ１５が搭載されており、それらの電気的接
続には、半田バンプ１６が用いられている。The first embodiment, as shown in FIGS. 1(a) and (b),
Mount island 1 for mounting lead frame 11 on board
Mounting chips 15 such as various IC chips are mounted on a silicon wiring board 13 consisting of a fine pattern of several microns width pasted on the silicon wiring board 2, and solder bumps 16 are used for electrical connection between them. ing.
又、リードフレーム１１と、シリコン配線基板１３との
電気的接続には、ボンディングワイヤ１４を使用してい
る。Further, a bonding wire 14 is used for electrical connection between the lead frame 11 and the silicon wiring board 13.
第２図（ａ）、（ｂ）は本発明の第２の実施例の平面図
及び断面図である。FIGS. 2(a) and 2(b) are a plan view and a sectional view of a second embodiment of the present invention.
第２の実施例は、第２図（ａ）、（ｂ）に示すように、
第１の実施例に加えて、更に、シリコン配線基板２３上
の所定の位置に、抵抗パターン２８とコンデンサパター
ン２９が作り込まれている。The second embodiment, as shown in FIGS. 2(a) and (b),
In addition to the first embodiment, a resistor pattern 28 and a capacitor pattern 29 are further formed at predetermined positions on the silicon wiring board 23.
以上説明したように本発明は、プリント配線基板の代わ
りにシリコン配線基板を用いることにより、配線幅を１
ケタ程度小さく出来る為、配線密度は飛躍的に向上する
。As explained above, the present invention uses a silicon wiring board instead of a printed wiring board to reduce the wiring width by 1.
Since it can be made an order of magnitude smaller, wiring density can be dramatically improved.
さらに、従来独立に作成しなければならなかった受動素
子チップもシリコン配線基板上に直接に、しかも、従来
のプロセス技術の転用で個々の素子単位に任意の位置に
パターンとして作り込むことが可能となる為、搭載チッ
プ数を１個から数個減少出来、従来、配線を引き回す上
で障害となっていたランドパターンを十分率さなものと
することができる。Furthermore, passive element chips, which conventionally had to be made independently, can now be fabricated as patterns directly on silicon wiring substrates, and in arbitrary positions for individual elements by reusing conventional process technology. Therefore, the number of mounted chips can be reduced from one to several, and the land pattern, which has conventionally been an obstacle in routing wiring, can be made sufficiently efficient.
以上の効果を総合して、実施例のトランスファーモール
ド型・但成集積回路装置は、従来のそれに比較して２〜
３倍程度の実装密度を実現できる効果がある。Taking all of the above effects into account, the transfer mold type integrated circuit device of the embodiment has a
This has the effect of realizing a packaging density about three times higher.
第１図（ａ）、（ｂ）は本発明の第１の実施例の平面図
及び断面図、第２図（ａ）、（ｂ）は本発明の第２の実
施例の平面図及び断面図、第３図（ａ）、（ｂ）は従来
の混成集積回路装置の一例の平面図及び断面図である。FIGS. 1(a) and (b) are a plan view and a sectional view of a first embodiment of the present invention, and FIGS. 2(a) and (b) are a plan view and a sectional view of a second embodiment of the present invention. 3A and 3B are a plan view and a sectional view of an example of a conventional hybrid integrated circuit device.
１．２１．３１・・・リードフレーム、１２，２２．３
２・・・基板搭載用マウントアイランド、１３．２３・
・・シリコン配線基板、３３・・・プリント配線基板、
１４．２４．３４・・・ボンディングワイヤ、１５，２
５．３５・・・搭載チップ、１６．２６・・・半田バン
プ、１７，２７．３７・・・トランスファーモールド樹
脂、２８・・・抵抗パターン、２９・・・コンデンサパ
ターン。1.21.31...Lead frame, 12,22.3
2...Mount island for board mounting, 13.23.
... Silicon wiring board, 33... Printed wiring board,
14.24.34...Bonding wire, 15,2
5.35... Mounted chip, 16.26... Solder bump, 17, 27.37... Transfer mold resin, 28... Resistance pattern, 29... Capacitor pattern.
Claims (2)
スファーモールドして成る混成集積回路装置に於いて、
前記配線基板としてシリコン基板を使用し、且つ、フリ
ップチップをバンプ接続した部分を有することを特徴と
する混成集積回路装置。(1) In a hybrid integrated circuit device formed by mounting a plurality of IC chips on a wiring board and performing transfer molding,
A hybrid integrated circuit device characterized in that a silicon substrate is used as the wiring substrate and has a portion in which a flip chip is bump-connected.
ンとして作り込まれている請求項１記載の混成集積回路
装置。(2) The hybrid integrated circuit device according to claim 1, wherein at least one passive element is formed as a pattern within the wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26969488A JP2663567B2 (en) | 1988-10-25 | 1988-10-25 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26969488A JP2663567B2 (en) | 1988-10-25 | 1988-10-25 | Hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02116152A true JPH02116152A (en) | 1990-04-27 |
| JP2663567B2 JP2663567B2 (en) | 1997-10-15 |
Family
ID=17475889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26969488A Expired - Lifetime JP2663567B2 (en) | 1988-10-25 | 1988-10-25 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2663567B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05190758A (en) * | 1992-01-09 | 1993-07-30 | Sharp Corp | Semiconductor device and manufacture thereof |
| US5365409A (en) * | 1993-02-20 | 1994-11-15 | Vlsi Technology, Inc. | Integrated circuit package design having an intermediate die-attach substrate bonded to a leadframe |
-
1988
- 1988-10-25 JP JP26969488A patent/JP2663567B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05190758A (en) * | 1992-01-09 | 1993-07-30 | Sharp Corp | Semiconductor device and manufacture thereof |
| US5365409A (en) * | 1993-02-20 | 1994-11-15 | Vlsi Technology, Inc. | Integrated circuit package design having an intermediate die-attach substrate bonded to a leadframe |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2663567B2 (en) | 1997-10-15 |
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