JPH02118729A - Information processor - Google Patents

Abstract

PURPOSE:To reduce the number of the dynamic steps of a micro program by holding instructions at the time of the access of a virtual register. CONSTITUTION:A processor part 3 outputs the address of the virtual register to an address signal line 6, and an address holding part 5 detects it to be an address output by an IO access instruction and holds the address. An interruption generation part 4 detects that the access instruction for the virtual register is performed, and generates interruption in the processor part 3. In an interruption routine, the address of the virtual register is read from the address holding part 5 and further the content of an instruction holding part 2 is read and which real register the program before interruption has used is informed, and the content of the virtual register is written into the real register. Thus, the number of the dynamic steps of the micro program operating in the interruption routine can be reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention uses virtual registers set on memory! The present invention relates to an information processing device accessed by an O access command.

[Prior Art] A virtual register is a register that was previously configured in hardware, but is set in memory. When reading a virtual register, an interrupt is generated by executing an IO access instruction, and the interrupt routine is executed. Transfers the data in the virtual register to the real register where it is stored.

In the conventional technology, a microprogram calculates the address of the IO access instruction based on the next address of the IO access instruction stored by hardware, that is, the return address from the interrupt, reads the IO instruction from the instruction memory, and stores the virtual The address of the real register that stores the data read from the register was calculated.

[Problems to be Solved by the Invention] The conventional virtual register reading method described above has the disadvantage that the number of dynamic steps of the microprogram operating in the interrupt routine increases in order to calculate the address of the real register.

[Means for Solving the Problems] An information processing device according to the present invention is an information processing device that accesses a virtual register set on a memory using a 0 access instruction, and generates an interrupt immediately after executing an IO access instruction. It has an interrupt generating means, an address holding means for holding the address of the virtual register, and an instruction holding means for holding the real register identification part in the IO access instruction.

[Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention.

The information processing apparatus of this embodiment includes a memory section 1 for holding instructions and data, an instruction holding section 2 for holding instructions read from the memory section 1, a processor section 3 for executing instructions, and a processor section 3 for executing instructions. An interrupt generation unit 4 that detects access to a virtual register and generates an interrupt, and a processor unit 3
It is composed of an address holding section 5 that holds virtual register addresses output by , an address signal line 6 , and a data bus 7 .

The operation of the information processing apparatus of this embodiment will be described below with reference to FIG.

When reading the virtual register, the processor section 3 requests the right to use the data bus 7 from the data bus management section (not shown).

Upon receiving permission for use from the data bus management section, it outputs the address of the virtual register to the address signal line 6. The address holding unit 5 detects that the address is output by an IO access command and holds the address. of course,
The address may be held only in the case of virtual register access.

Now, the interrupt generating section 4 detects that the instruction to access the virtual register has been executed, and generates an interrupt to the processor section 3.

When the data bus management section ends the bus access and causes the processor section 3 to take over the dummy data, the IO access command ends and the interrupt is accepted.

In the interrupt processing routine, the address of the virtual register is read from the address holding section 5, converted to an address on the memory section 1, and the contents of the memory section 1, that is, the contents of the virtual register are taken out. Furthermore, the contents of the instruction holding unit 2 are read, it is known which real register was used by the program before the interrupt, the contents of the virtual register are written to the real register, and the interrupt routine is ended.

As a result of the above, the contents of the virtual register can be read into the target real register.

Although it is obvious, the instruction holding section 2 only needs to hold the real register address identification section.

[Effects of the Invention] As described above, the present invention has the effect of reducing the number of dynamic steps of a microprogram by retaining instructions during virtual register access.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Memory part, 2... Instruction holding part, 3... Processor part, 4... Interrupt generation part, 5... Address holding part, 6... Address signal line, 7... data bus.

Claims (1)

[Scope of Claims] 1. In an information processing device that accesses a virtual register set on a memory using an IO access instruction, an interrupt generating means that generates an interrupt immediately after executing the IO access instruction; An information processing device comprising: address holding means for holding an address; and instruction holding means for holding a real register identification part in the IO access instruction.