JPH0212306A - Output driver for programmable controller - Google Patents

Abstract

PURPOSE:To reduce the relay driving current by using a clock generator to produce a clock having the prescribed duty and flowing the relay driving current only in an ON period of said clock. CONSTITUTION:The output data (a) given from a CPU 1 is stored in a latch 2 and the latch data (d) is given to a driver 13. Then a driving current flows to a photodiode 5a via a driver 13 of a 2-input NAND gate type only in an ON period of a clock (e). In other words, the dynamic drive is applied to a relay 4 and the average driving current reduces according to the duty of the clock (e). For instance, the average driving current is cut down to 1/5 when said duty is set at 20%. In such a way, the relay driving current is reduced.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to an output drive device for a programmable controller, and more specifically, it has a function of converting an internal signal to an external circuit drive level isolated by a photocoupler and transmitting the signal. This is suitable for application to an output device of a programmable controller.

(Prior Art) As this type of output device, the one shown in FIG. 4 is conventionally known. In this device, the latch 2 of the output section 7 receives the output data a from the programmable controller Cr'L11 as a latch signal. The latch data d of the latch 2 is applied via the driver 3 to the photodiode 5a of the photocoupler 5, which is a component of the relay 4, and a drive current determined by the current limiting resistor 6 flows to the phototransistor. 5b open (off)/close (on). The reset signal C is used to reset the latch 2 to the initial state when the device is powered on/off or when an abnormality occurs.

In such an output drive device, the drive current when the relay 4 is closed (on) always flows, and the relay drive current of the entire programmable controller is the drive current per relay point and the closed (on) state of the relay 4. on) is multiplied by the number of points.

Incidentally, programmable controllers are desired to have low internal current consumption in order to be miniaturized and to reduce power consumption, and in particular, it is desired to reduce the output drive current that accounts for most of the current consumption.

(Problem to be Solved by the Invention) However, the number of relays in a programmable controller is generally from several tens to several hundreds, and the conventional configuration described above has the problem that the overall relay drive current increases. . That is, for example, if the drive current per relay is 5mA and the number of relays is 500, the total relay drive current is 5mA x 500-2.
This is because it can reach 58.

SUMMARY OF THE INVENTION An object of the present invention is to provide an output drive device that eliminates such problems and configures a power-saving output device that requires less drive current.

[Means to solve the problem]

To this end, the present invention provides a control signal generating means for generating a control signal to be supplied to an output device of a programmable controller, which has a function of insulating internal signals with a photocoupler, converting them to an external circuit drive level, and transmitting the signals, and a predetermined a clock generating means for generating a Dudy clock; a signal storing means for temporarily storing the signal from the control signal generating means; and an output means for intermittently outputting the control signal output from the signal storing means in accordance with the clock; A plurality of relays are driven based on intermittent output from the output means.

(Function) In the present invention, the response time of a photocoupler used in a relay mainly for insulation and voltage level conversion is divided into an off-on response time (ton) and an on-off response time (torr).
) and t by an order of magnitude. Focusing on the characteristic that rt is large,
In short, it is a drive that supplies drive current only for the time required for the photocoupler to turn on completely when the relay is on, and once the photocoupler is turned on, it supplies drive current periodically until the photocoupler turns off. Dynamically drives the photocoupler. This reduces the average drive current.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an output unit 17 according to an embodiment of the present invention, and corresponding parts are given the same reference numerals as those in FIG. The difference between this example and the configuration shown in FIG. 4 is that a driver 13 in the form of a two-man NAND gate is provided instead of the driver 3, and a predetermined on-off period Nori-lock e from the clock generator 8 is provided to the driver 3. The reason is that the input is made to one side. Here, the on-off period of the clock e is the response time t of the rise and fall of the photocoupler 4. The following settings are made in consideration of TI + jof f.

(1) Use a photocoupler to control the on-period of clock e. , be sufficiently larger than .

(2) The off-period of clock e is set to t of the photocoupler. 11
Make it sufficiently smaller.

Photocoupler t. n and t. Comparing with te, joff is orders of magnitude larger, so clock e on-
The off-period ratio, that is, the duty, is determined by [on-period/(on-period+off-period)]xlOOk, and is a sufficiently small value. For example, ton +++5μs, clock e
Assuming that the on period of = 20 μs, torr-21) Q μs, and the off period of clock e = 80 μs, the duty of clock e is [20/(20+80)] x 100-20
It becomes.

According to the configuration shown in FIG. 1, output data a from the CPUI is stored and held in the latch 2, and latch data d is
3 can be considered in the same way as in the conventional example, but only during the ON period of clock e, two-man powered NAN
This differs from the conventional example in that the D-gate type driver 13 applies a driving current force 9 to the photodiode 5a. In other words, the relay 4 is driven dynamically, and the average drive current decreases according to the duty of the clock e.

That is, for example, if the duty is set to <2094 as described above, the average drive current becomes 115, which is the conventional value.

The operation delay of relay 4 in response to output data rewriting by CPIII to latch 2 is determined by the cycle of clock e, but it is approximately 100 μs or less, so the operation speed of external equipment connected to relay 4 and the control system centered on GPUI are determined by the cycle of clock e. Considering the operating speed of , this is not a practical problem. Further, the drive current of the relay 4 flows intermittently only when the output is on, but since the on-off period of the clock e is set as in the above-mentioned items (1) and <2), the phototransistor 5b is closed ( The relay 4 remains on), and no chattering (repetitive on/off) occurs in the relay 4.

Note that it is sufficient that one clock generator 8 is provided in the programmable controller, and can be connected to a plurality of output sections 7 in common.

FIG. 2 shows an output section 27 according to another embodiment of the invention.

The difference from FIG. 1 is that the driver 23 is a simple NOT element, and that the clock e from the clock generator 8 is
Accordingly, the transistor 9 as a semiconductor switch is intermittently turned on and off, and an opening current is supplied to the photodiode 5a of the photocoupler 5 only when the transistor 9 is turned on. However, resistor 6
b is used to limit the base current of the transistor 9, and the resistor 6C is used to prevent the transistor 9 from being erroneously turned on due to leakage current. The duty of the clock e is the same as in FIG. 1, but since the transistor 9 as a switch is of PNP type as shown in the figure, the phase (voltage logic) of the clock e is opposite to that in FIG.

With the configuration shown in FIG. 2, it is possible to reduce the relay drive current as in the case of FIG. 1.

Next, the operations in FIGS. 1 and 2 will be supplemented with the explanation using FIG. 3.

At time t0, the reset signal C becomes inactive, and the reset for the output section 7 is released. Since the latch 2 is reset while the reset signal C is active, the latch data d is inactive. The clocks e2 (corresponding to FIG. 1) and e3 (corresponding to FIG. 2) have a predetermined duty, [co
n/(Con"Corp) ] x 1oox. At time, the output data a from the CPUI is stored and held in the latch 2 at the trailing edge of the latch signal d, and the latch data d becomes active.

Relay g! A! In the current generator, the latch data d flows intermittently only during the ON period C0° of the clock e2 or e during the active period, and the first relay drive current begins to flow at time t2. As a result, t from time t2. When n time (on-response time of the odocoupler) has elapsed, the transistor 5b
is closed (turned on), and the collector-emitter voltage vcg decreases. The clock-on period C0° is the photocoupler's on-response time t. Since it is set to be thicker than n, the relay drive current IF continues to flow even after the phototransistor 5b is closed (turned on).

At time t3, the clock e2 or e shifts from on to off, and therefore the relay drive current IF is cut off.
After that, the phototransistor 5b remains closed (on) (VC
E is a low potential). The clock off period Coff is the off response time t of the photocoupler. Since it is set sufficiently smaller than ff, the phototransistor 5b at time t4
The relay drive current changes again before it opens (off) (VCE becomes high potential)! , is supplied. In this manner, the relay 4 is dynamically pulse-driven thereafter to maintain the closed (on) state of the phototransistor 5b.

At time t, output data a is rewritten to latch 2 by the CPU. This causes the latch data d
becomes inactive, so even if the clock e2 or e3 is turned on thereafter, the relay drive current IP will not flow. The phototransistor 5b has a relay drive current 1 just before the rising of time ts.
After the last pulse of the r pulse train turns off. After the ff time (off response time of the photocoupler) has elapsed, the VCE becomes off, and VCE shifts to a high potential.

(Effects of the Invention) As described above, according to the present invention, a clock generator that generates a clock with a predetermined duty is provided, and the relay drive current is configured to flow only during the ON period of this clock. The drive becomes dynamic drive, which has the effect of reducing the average drive current.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an output driving device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of an output driving device according to another embodiment of the present invention, and FIG. 3 is a circuit diagram of an output driving device according to another embodiment of the present invention. FIG. 4 is a circuit diagram of a conventional output drive device. 1...cpu. 2...Latch, 3.13.23...Driver, 4...Relay 5...Photocoupler, 7.17.27-...Output section, 8...Clock generator, 9...・Transistor. Figure 2 Figure 3

Claims (1)

[Claims] 1) Control signal generating means for generating a control signal to be supplied to an output device of a programmable controller having a function of insulating an internal signal with a photocoupler, converting it to an external circuit drive level, and transmitting the signal; Clock generation means for generating a clock of a predetermined duty; Signal storage means for temporarily storing the signal from the control signal generation means; Intermittently generating the control signal outputted from the signal storage means in accordance with the clock. An output drive device for a programmable controller, comprising: an output means for outputting an output; and a plurality of relays driven based on intermittent outputs from the output means. 2) Regarding the on-off period ratio of the clock, the on-period is set to be sufficiently larger than the on-response time of the photocoupler, and the off-period is set to be sufficiently smaller than the off-response time of the photocoupler. Item 2. An output drive device for a programmable controller according to item 1.