JPH0212329A - Program execution control method - Google Patents

Abstract

PURPOSE:To prevent the runaway of each control program in a computer system consisting of plural memories by executing the control program stored in each memory after the adaptable state is decided among those memories. CONSTITUTION:In a computer system consisting of plural memories, the hardware includes a microcomputer 10, a memory 10a, a 1st ROM 11, a 2nd ROM 12, a RAM 13, an input/output terminal equipment 14, and a fault informing signal generator 15. Then the proper identification information is previously stored in the memories 11 and 12 respectively. At the same time, the combination states of control programs stored in both memories 11 and 12 are collated with each other. Thus the start control is given to the control programs which are read out of the memories 11 and 12. As a result, the system runaway can be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a computer system having a microprocessor that controls peripheral devices based on control programs individually stored in a plurality of memories.

(Prior Art) FIG. 7 is a block diagram illustrating the configuration of a conventional computer system, in which 51 is a microcomputer composed of a microprocessor (for example, the μPD series manufactured by NEC Corporation), and a read-only memory (ROM). ) 52 or read-only memory (ROM) 53 based on the control program stored in advance, input/output terminal equipment (I/O
lo) Overall control of 55. Reference numeral 56 denotes an address bus which transfers the address output from the microcomputer 51 to the ROM 52. ROM53. RAM 54° Outputs to input/output terminal equipment (Ilo) 55, etc. Reference numeral 57 denotes a data bus for transmitting human output data to the microcomputer 51 and address bus 56. ROM 52 connected via data bus 57.
ROM53°RAM54. Input/output terminal equipment (Ilo) 5
5 mutually send and receive data.

For example, when the microcomputer 51 executes a control program stored in the ROM 52, it outputs a unique read address assigned to the ROM 52 to the address bus 56, and executes the control program read from the ROM 52 via the data bus 57. The input/output terminal equipment (Ilo) 5 receives the
5b), and sends predetermined data to the input/output terminal device (Ilo) 55.

[Problem to be solved by the invention]

However, to enable this kind of program execution, the ROM 52. If the combination of control programs stored in the ROM 53 is not appropriate, for example, the combination of control programs stored in the ROM 52.
If there is a shared address in the ROM53,
Since the control program to be read is in an uncertain state,
If the system stops working properly, or in the worst case, the system goes out of control, the input/output terminal equipment (I 10 )
There were serious problems such as erroneous operation of the 55, exposing workers to unexpected situations.

In the future, when setting multiple control boards with new ROMs installed in an existing computer system to expand or change control functions, the system will become extremely unstable unless the above problems are solved. As the flexibility of
System development costs have become extremely important, and improvements are awaited.

This invention was made to solve the above problems, and it is possible to store unique identification information in a plurality of memories in advance, and to compare and determine the combination state of control programs stored in each memory. The purpose of the present invention is to obtain a program execution control method that can safely start and control control programs read from multiple memories without causing system abnormalities.

(Means for Solving the Problems) The program execution control method according to the present invention includes an identification code reading process of reading out a program identification code stored at a predetermined address of each memory each time a memory access occurs, and A determination process that compares each program identification code obtained through the process and determines the suitability for starting the combination with a predetermined control program stored in each memory, and a This method includes a program startup restriction process that restricts the startup of a part or all of a predetermined control program stored in the computer.

Furthermore, a notification signal generation process may be added that generates a combination activation failure notification signal when the combination activation with each predetermined control program stored in each memory is determined to be an error in the determination process.

(Operation) In the present invention, each read-only memory access is performed by reading out the program identification code stored at a predetermined address in each read-only memory, and each program identification code obtained by this identification code reading process. are compared to determine suitability of combination activation with a predetermined control program stored in each read-only memory. Then, based on the verification result of this determination process, activation of some or all of the predetermined control programs stored in each read-only memory is restricted. At this time, if it is determined that the combination activation with each predetermined control program stored in each read-only memory is an error, a combination activation failure notification signal is generated.

(First Embodiment) FIG. 1 is a hardware configuration diagram to which a program execution control method is applied, showing an embodiment of the present invention. 10 is a microcomputer, and the control program stored in the first ROM 11 or the second ROM 12 is Based on input/output terminal equipment (
Ilo) 14 is generally controlled. 10a is memory,
The control procedure shown in FIG. 3 is stored. 16 is an address bus which transfers the address output from the microcomputer 10 to the first ROM 11. 2nd ROM12. RAM13
．． Output to input/output terminal equipment (Ilo) 14, etc. In addition,
A unique program identification code for identifying the stored control program is written in advance at a predetermined address in the first ROM 11 or the second ROM 12.

17 is a data bus, which transfers input/output data to the microcomputer 1Q and the address bus 16. The first ROM 11 . connected via the data bus 17 . 2nd ROM12. RAM1
3. Mutual transmission and reception is performed between the input/output terminal equipment (Ilo) 14. Reference numeral 15 denotes a failure notification signal generator, which limits the activation of part or all of the predetermined control programs stored in the first ROM 11 and the second ROM 12 when activation in combination with each predetermined control program is determined to be an error. Generates a fault notification signal.

FIG. 2 is a flowchart illustrating a program execution control method showing an embodiment of the present invention.

Note that (1) to (7) indicate each step. Further, in this embodiment, the number of ROMs is not limited to two.

The process when the number of ROMs is "2" will be described in detail below.

First, the CPU of the microcomputer 10 is connected to the memory 10.
Based on the contents of a, judge whether the number of ROMs to be used is "2" or more (1). If no, proceed to step (5).
), if YES, the microcomputer 1o accesses the first ROM 11 and determines whether the identification data is set in a predetermined area of the first ROM 11 (2); if YES, the microcomputer 1o
accesses the second ROM 12 to determine whether identification data is set in a predetermined area of the second ROM 12 (3), and if YES, the microcomputer 10 accesses the program identification code stored in the predetermined area of the first ROM 11 and the second ROM 12. read out the program identification code stored in a predetermined area of
If o, a normal processing routine is executed to execute normal program execution processing based on the control program stored in the first ROM II or the second ROM 12 (5).

On the other hand, if the determinations in steps (2) and (3) are NO and the determination in step (4) is YES, the failure notification signal generator 15 is activated (6) and a failure notification signal is sent to forcibly terminate the system processing by the microcomputer 10. is output, the termination processing routine is executed (7), and the processing is terminated. In the above embodiment, the case where the control procedure of the embodiment is stored in the memory 10a has been described, but the first RO
The configuration may be such that the information is stored in either the M11, the second ROM 12, or the RAM 13.

(Second Embodiment) FIG. 3 is a hardware configuration diagram to which a program execution control method is applied showing another embodiment of the present invention, in which 20 is a master microcomputer unit, a microcomputer 21. ) has stored the control procedure shown in
OM21a, first ROM22. 2nd ROM23. RAM
24. Input/output terminal equipment (Ilo)25. The microcomputer 21 is connected to an address bus 35. The microcomputer 21 . 1st ROM22. 2nd ROM23.
RAM24. Input/output terminal equipment (Ilo)25. A fault notification signal generator 26 is connected. Reference numeral 30 denotes a slave microcomputer unit, which is configured so as to be able to perform data processing with the master microcomputer unit 20 via communication lines 40 and 41.

Note that the slave microcomputer unit 30 is
Microcomputer 31. ROM 31a, ROM 32. which stores the control procedure shown in FIG. 4(b). RAM
33. Consists of input/output terminal equipment (Ilo) 34, etc.
ROM321. :Controls the input/output terminal W (Ilo) 34 based on the stored control program. In addition, upper memory 1 ROM22. 2nd ROM23. ROM3
2 has unique program identification code data stored in advance at a predetermined address.

FIGS. 4(a) and 4(b) are flowcharts illustrating a program execution control system showing another embodiment of the present invention. Note that (1) to (10) and (11) to (18) indicate each step. In particular, each step (1) to (10) corresponds to a processing procedure executed by the microcomputer 21 of the master microcomputer unit 20, and each step (11) to (18) is processed by the microcomputer 31 of the slave microcomputer unit 3o. Corresponds to the procedure to be followed.

[Mask Side] First, the microcomputer 21 waits to receive identification data information of the ROM 32 used by the slave microcomputer unit 3o via the communication line 41 based on the contents of the ROM 21a. The CPU receives and stores the data (stored in the internal memory within the microcomputer 21), and the microcomputer 21 accesses the first ROM 22 to receive the first data.
It is determined whether identification data is set in a predetermined area of the ROM 22 (2). If YES, the microcomputer 21 accesses the first ROM 22 and reads the second R
Determine whether identification data is set in the predetermined area of OM23 (3), if YES, communication line 4
4) If YES, the microcomputer 21 selects the program identification code stored in the predetermined area of the second ROM 23 and the program stored in the predetermined area of the second ROM 23. The identification code and the received identification data are read out and stored in the first ROM 22. 2nd ROM23
．． Determine whether starting a combination of programs stored in the ROM 32 results in an error startup by referring to the combination table provided in the ROM 2Ia or by comparing it with the identification information imported into the CPU5), No.
If so, the microcomputer 21 of the master microcomputer unit 20 should execute a processing continuation routine in which the microcomputer 21 of the master microcomputer unit 20 sends a signal to the microcomputer 31 of the slave microcomputer unit 3o via the communication line 40 to permit processing to continue 6). Execute the routine (7) On the other hand, if the determination in steps (2) to (4) is NO and the determination in step (5) is YES, the microcomputer 21 of the master microcomputer unit 2o
executes a termination transmission routine to forcibly terminate processing to the microcomputer 31 in the slave microcomputer unit 30 via the communication line 40 (
8).

Next, activate the failure notification signal generator 26 (9)
A failure notification signal for forcibly terminating the system processing by the microcomputer 21 is output, and the termination processing routine is executed (10), thereby terminating the processing.

[Slave side] First, the microcomputer 31 accesses the ROM 32 according to the procedure stored in the ROM 31a and determines whether or not identification data is set11), Y
If it is ES, the identification data is stored in RAM3 as identification data information.
Set it to 3 (12), proceed to step (14) and onwards, and
If O, the unset information is set in the RAM 33 as identification data (13).

Next, R is sent to the microcomputer 21 of the master microcomputer unit 20 via the communication line 41.
A transmission routine for transmitting identification data information of AM33 is executed (14).

Next, the receiver waits to receive a subsequent processing instruction from the microcomputer 21 of the master microcomputer unit 20 (15), and upon receipt, the receiver judges whether the received instruction is an instruction to continue processing (16), Y
If it is ES, perform the normal processing routine described above (17)
, if No, the termination processing routine is executed (18), the processing of the microcomputer 31 is forcibly terminated, and the processing is terminated. In addition, in the above embodiment, ROM21a and ROM3
Although we have explained the case where the control procedure is stored in 1a,
The above control procedure may be stored in a separate ROM, RAM, or the like.

[Third Embodiment] FIG. 5 is a hardware configuration diagram to which a program execution control method is applied, showing still another embodiment of the present invention, and the same components as in FIG. 3 are given the same reference numerals. .

In this figure, 29 is a reset signal, and signal line 4
The identification data stored in the ROM 32 received via the first ROM 22. When the processing by the microcomputer 31 is forcibly terminated in accordance with the comparison result with the identification data stored in the second ROM 23, it is outputted from the microcomputer 21 via an independent reset line.

FIGS. 6(a) and 6(b) are flowcharts illustrating a program execution control system showing another embodiment of the present invention. Note that (1) to (9) and (11) to (15) indicate each step. In particular, each step (1) to (9) corresponds to a processing procedure executed by the microcomputer 21 of the master microcomputer unit 20, and each step (11) to (15) is processed by the microcomputer 31 of the slave microcomputer unit 30. Corresponds to the procedure to be followed.

[Master side] First, the microcomputer 21 waits to receive the identification data information of the ROM 32 used by the slave microcomputer unit 30 via the communication line 41 (1), and when it receives it, the microcomputer 21 switches to the first R.
Access the OM22 and determine whether identification data is set in a predetermined area of the first ROM22.
), if YES, the microcomputer 21 is ilRO
Access M22 and determine whether identification data is set in a predetermined area of the second ROM23 3)
If YES, determine whether the identification data information received via the communication line 41 is identification data 4), YES
If S, the microcomputer 21 reads out the program identification code stored in a predetermined area of the second ROM 23, the program identification code stored in a predetermined area of the second ROM 23, and the received identification data, and
ROM22, second ROM23. It is determined whether starting the combination of programs stored in the ROM 32 results in an error starting (5), and if no, the normal processing routine is executed (6).

On the other hand, if the determination in steps (2) to (4) is NO and the determination in step (5) is YES, the microcomputer 21 of the master microcomputer unit 20
sets the reset signal 29 to the H level state (7) and causes the microcomputer 31 in the slave computer unit 30 to execute a termination transmission routine for forcibly terminating the process.

Next, the failure notification signal generator 26 is activated (8), a failure notification signal for forcibly terminating the system processing by the microcomputer 21 is outputted, and the termination processing routine is executed (9), thereby terminating the process.

[Slave side: First, the microcomputer 31 accesses the ROM 32 to determine whether or not identification data is set (11). If YES, the identification data is set as identification data information (12), and steps (14) and thereafter are performed. Go ahead, NO
If so, set the unset information as identification data (13)
.

Next, a transmission routine for transmitting identification data information to the microcomputer 21 of the master microcomputer unit 2o via the communication line 41 is executed (14).
). Next, the normal processing routine described above is performed (15
).

In the above embodiment, the present invention is applied to a case where the microcomputer and the ROM have an independent hardware configuration, but it goes without saying that the present invention can also be applied to a microprocessor with a built-in ROM. The program does not have to be a ROM, but may be a storage medium such as an optical disk (including, for example, a CDROM) or a floppy disk.

〔Effect of the invention〕

As explained above, the present invention includes an identification code reading process for reading out a program identification code stored at a predetermined address in each memory each time a memory access occurs, and each program identification code obtained by this identification code reading process. A determination process that compares and determines the compatibility of the combination activation with a predetermined control program stored in each memory, and one of the predetermined control programs stored in each memory based on the verification result of this determination process. Since program startup restriction processing is executed to restrict the startup of some or all of the programs, when a computer system consisting of multiple memories is constructed, the compatibility between each memory is always determined before the data is stored in each memory. Since the specified control programs are executed, it is possible to prevent each control program from running out of control, and also to prevent malfunctions of peripheral devices controlled by each control program, making it possible to build a highly reliable system at a low cost. .

Also, judgment! By executing a notification signal generation process that generates a combination activation failure notification signal when combination activation with each predetermined control program stored in each memory 1 is determined to be an error due to the In a computer system consisting of the following, it is possible to notify that the program cannot be started before the program is executed, and it has excellent effects such as being able to confirm the occurrence of system abnormality.

[Brief explanation of the drawing]

Fig. 1 is a hardware configuration diagram to which a program execution control method is applied, showing an embodiment of the present invention, Fig. 2 is a flowchart explaining the program execution control method showing an embodiment of the invention, and Fig. 3 is a diagram of the invention. FIG. 4(a) is a hardware configuration diagram to which a program execution control method is applied showing another embodiment of
, (b) is a flowchart explaining a program execution control method showing another embodiment of the present invention, FIG. 5 is a hardware configuration diagram to which a program execution control method is applied showing still another embodiment of the invention, Figure (a). (b) is a flowchart illustrating a program execution control method showing another embodiment of the present invention, and FIG. 7 is a block diagram illustrating the configuration of a conventional computer system. In the figure, 10 is a microcomputer, 11 is the first ROM
, 12 is a second ROM, and 13 is a RAM. 14 is an input/output terminal device, 15 is a failure notification signal generator, 1
6 is an address bus, and 17 is a data bus. Figure 1 Figure 2 Figure (a) Figure (a) Figure (b)

Claims (2)

[Claims] (1) In a computer system that has a plurality of memories in which predetermined control programs are stored in advance, and in which a microcomputer controls peripheral devices based on the predetermined control programs stored in these memories, each time a memory access occurs, , an identification code reading process of reading out a program identification code stored at a predetermined address of each memory, and each program identification code obtained by this identification code reading process are compared to identify the predetermined control program stored in each memory. and a program activation restriction process that restricts activation of some or all of the predetermined control programs stored in each memory based on the verification result of this determination process. A program execution control method characterized by: (2) The feature includes a notification signal generation process that generates a combination activation failure notification signal when the combination activation with each predetermined control program stored in each memory is determined to be an error. The program execution control method according to claim (1).