JPH0212423B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system for monitoring the bit error rate of a transmitted signal in a binary digital signal transmission system.

A configuration diagram of a conventional example using a biphase code is shown in FIG. In the figure, 1, 13, 14, 15 are terminals, 2 is a biphase encoding circuit, 3 is a transmission line drive circuit, 4 is a transmission line, 5 is a reception amplifier circuit, 6 is an identification regeneration circuit, 7 is a timing regeneration circuit, 8 is sampling circuit 1, 9 is sampling circuit 2, 1
0 is a block synchronization circuit, 11 is a bit error rate calculation circuit, and 12 is a comparison circuit.

Transmission data is input from an input terminal 1 to a biphasic encoding circuit 2. The transmission line driving circuit 3 drives the transmission line 4 according to the input signal from the biphasic encoding circuit 2. After the signal propagates through the transmission line 4, it is received and amplified by the reception amplifier circuit 5, and outputted to the identification reproduction circuit 6 and the timing reproduction circuit 7.

The timing recovery circuit 6 extracts a clock twice the transmission bit rate from the output of the reception amplifier 5,
It is output to the identification reproducing circuit 6 and the block synchronization circuit 8. The identification and regeneration circuit 6 samples the input from the receiving amplifier 5 using the input from the timing regeneration circuit 7, regenerates a binary digital signal, and outputs it to the sampling circuit 18, the sampling circuit 29, and the block synchronization circuit 10. The block synchronization circuit 10 divides the frequency of the input from the timing regeneration circuit 7 by two, and receives the result from the identification regeneration circuit 6. It is synchronized to the 2-bit break of the biphase encoded data, and outputs the timing synchronized with the first half bits to the sampling circuit 18, and the timing synchronized with the second half bits to the sampling circuit 29 and the code error rate calculation circuit 11. .

The sampling circuit 18 samples the input from the identification/reproduction circuit 6 with the input from the block synchronization circuit 10 and sends the result to the comparator 12 and the inverting output terminal 1.
Output to 3.

Since the sampling circuit 18 samples the first half bits in biphase encoding, it outputs an inverted signal of the transmitted data. sampling circuit 29
Of the input from the discrimination/reproduction circuit 6, the second half bits in biphase encoding are sampled by the input from the block synchronization circuit 10, and the output is output to the comparison circuit 12 and the positive phase output terminal 14. The sampling circuit 18 samples the latter half bits in biphase encoding, and therefore outputs a positive phase signal of the transmission data. In bi-phase encoded data, the relationship between the first half bit and the second half bit is inverted unless a code error has occurred, so if the two match, it means that a code error has occurred. Comparison circuit 12 receives input from sampling circuit 18 and sampling circuit 29
If the inputs from the two match, an error detection pulse is output to the error rate calculation circuit 11. The error rate calculation circuit 11 counts the count value of the sampling pulse inputted from the block synchronization circuit 10 and the error detection pulse inputted from the comparison circuit 12, and divides it by half.
The code error rate is calculated from the ratio of the value of , and is output to the terminal 15. Setting the count value of detected pulses to 1/2 is
This is because the signals output to terminal 13 and terminal 14 are equally erroneous.

It is preferable for code error rate monitoring to detect a state in which the transmission system is tending to deteriorate rather than a state in which the transmission system has deteriorated. The error rate status will be monitored. Usually, terminal 1
Since the bit error rate of the signal output from 3 and 14 is very small, in order to accurately calculate the bit error rate, it is necessary to count the sampling pulses and error detection pulses over a long period of time using a multi-stage counter. There must be. This has resulted in disadvantages such as an increase in circuit scale and a slow response to code error rate deterioration.

In order to solve these drawbacks, this invention connects a low frequency cutoff circuit to the transmission system, and when intersymbol interference is generated due to low frequency cutoff, the first half of the biphase encoded signal and the second half of the bit are separated. With bits, the bit error rate can be quickly monitored using a small-scale circuit by taking advantage of the fact that the amount of intersymbol interference varies.

FIG. 2 shows a configuration diagram of an embodiment of the present invention. In the figure, 15a is a reception amplifier circuit 1, 15b is a reception amplifier circuit 2, and 16 is a low frequency cutoff circuit. FIG. 3 is an eye pattern diagram of a biphase encoded signal. FIG. 4 is a diagram showing the relationship between the code error rate and the low cutoff frequency.

A low frequency cutoff circuit 16 connected to the next stage of the reception amplification circuit 15a generates intersymbol interference due to low frequency cutoff in the signal output from the reception amplification circuit 15a. FIG. 3 shows an eye pattern diagram at this time. In a biphase encoded signal, the first half bits experience greater intersymbol interference than the second half bits due to low frequency cutoff. Low frequency cutoff circuit 1
The output of 6 is amplified again by the reception amplification circuit 25b and output to the identification regeneration circuit 6 and the timing regeneration circuit 7.

In the output of the identification and reproducing circuit 6, the first half bits are as follows.
The bit error rate is higher than that of the latter bits. The low frequency cutoff frequency of the low frequency cutoff circuit 16 is expressed by a parameter K normalized by the transmission data bit rate, and the relationship between the code error rate of the first half bit and the second half bit with respect to the parameter K is shown in FIG. The figure explains the case where the code error rate is 10 ^-9 when there is no intersymbol interference. For example, if the cutoff frequency of the low frequency cutoff circuit 16 is chosen to be K=0.1, the first half bits will be 6.3×10 ^-6 and the second half bits will be 1.2×10 ^-9.
The code error rate is . The second half of the bits sampled by the sampling circuit 29 have almost no increase in error rate due to low frequency cutoff. In the comparison circuit 12,
The input from the sampling circuit 29 and the input from the sampling circuit 18 are compared, and if they match, the code error detection pulse is sent to the error rate calculation circuit 1.
The first half of the bits input from the sampling circuit 18 to the comparator circuit 12, which outputs to 1, has ¹⁰³ times more code errors than the second half.
The code error rate calculation circuit 11 can calculate the code error rate in a short time using a small scale counter. At this time as well, a good received signal with very few code errors is output from the positive phase output terminal 14.

The code error rate obtained by the code error rate calculation circuit 11 is the code error rate of the first half bits. Since there is a relationship between the bit error rate of the first half and the bit of the second half, by preparing a calibration table or the like in advance, it is possible to estimate the bit error rate of the second half from the bit error rate of the first half. If signal attenuation or noise increase occurs in the transmission system, a change in the value calculated by the bit error rate calculation circuit 11 can be detected in a short time. However, at this time, the output from the positive-phase output terminal 14, which is the sampling result of the latter half of the bits, has a line quality that can be used sufficiently, so the measured value from the bit error rate calculation circuit 11 is used as a signal indicating the deterioration tendency of the transmission system. can.

In addition, although the case where the low frequency cutoff circuit 16 is connected between the reception amplifier circuit 15a and the reception amplifier circuit 25b has been described above, it can be connected anywhere between the identification regeneration circuit 6 and the transmission line drive circuit 3. A similar effect can be obtained. Further, although the transmission system is not limited, it can be applied to either electric cable transmission or optical fiber transmission.

As described above, according to the code error rate monitoring system according to the present invention, a biphasic code is used as a transmission path code, and a low frequency cutoff circuit is connected to the transmission system to generate intersymbol interference, thereby making it possible to This has the effect that the code error rate can be measured and predicted in a short time using a small-scale circuit without deteriorating the error rate.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a conventional code error rate monitoring method, FIG. 2 is a block diagram of an embodiment of a code error rate monitoring method according to the present invention, and FIG. 3 is a block diagram of an embodiment of a code error rate monitoring method according to the present invention. The eye pattern diagram of the encoded signal, FIG. 4, is a diagram showing the relationship between the code error rate and the low frequency cutoff frequency. In the figure, 2 is a biphase encoding circuit, 8 is a sampling circuit 1, and 9 is a sampling circuit 2, 10.
11 is a block synchronization circuit, 11 is a bit error rate calculation circuit, and 16 is a low frequency cutoff circuit. It should be noted that the same or corresponding parts in the figures are indicated by the same reference numerals.

Claims (1)

[Claims] 1. A biphasic encoding circuit that converts 1-bit transmission data A into 2-bit data A or A that is inverted with respect to each other, and the output of the encoding circuit as input,
a transmission line drive circuit that outputs a signal to the transmission line, a transmission line, a reception amplification circuit that receives and amplifies the transmission line output, an identification reproduction circuit that samples the reception amplifier circuit output and reproduces binary digital data, and the identification 2 encoded on the transmitting side using the reproduction circuit output as input
Two sampling circuits that sample the first half and the second half of bit data, and code error rate calculation that calculates the error rate of received data by detecting whether the outputs of the sampling circuits are inverted with each other. A code error rate monitoring method for a binary digital transmission system, comprising: a low frequency cutoff circuit that further generates a low frequency cutoff distortion between the identification reproduction circuit and the transmission path drive circuit. A code error rate monitoring method that uses