JPH0118607B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an error detection method that can detect transmission errors with a simple configuration in a data transmission method using mB1C codes. be.

[Conventional technology]

Various code formats have been proposed for transmission error detection. For example, mB1P code, mB1C code, etc. are known. The former mB1P code is a code format in which a parity bit P is added to m-bit data to make it (m+1) bits, as shown in FIG.
Even parity is used in which the parity bit P is determined so that there is an even number of "1"s among (m+1) bits.

In data transmission using this mB1P code, transmission errors can be detected on the receiving side using the configuration shown in FIG. 6, for example.
That is, received data and a clock signal are applied to input terminals 31 and 32, respectively, received data synchronized with the clock signal from an AND circuit 33 is applied to a clock terminal C of a flip-flop 34, and a terminal output is applied to a data terminal D. Therefore, the inversion operation is performed for each “1” of received data.
If the Q terminal output in the initial state is “1”, (m+
1) Every time a bit is received, the Q terminal output becomes "1", which is the same as the initial state. “1” of m bits of data
When the probability of occurrence of is 1/2, flip-flop 3
By outputting the Q terminal output of No. 4 to the output terminal 36 via the low-pass filter 35, the DC level becomes high level if there is no transmission error.

FIG. 7 is an explanatory diagram of the operation, and as shown in a,
Q of flip-flop 34 for every (m+1) bits
The terminal output is the same as the initial state, for example "1",
When a 1-bit transmission error occurs as shown by E, there will be an odd number of "1"s among (m+1) bits, so the Q terminal output of the flip-flop 34 will be:
It becomes "0" after receiving (m+1) bits. If there is no transmission error thereafter, the Q terminal output of the flip-flop 34 becomes "0" for every (m+1) bits, and if there is a transmission error, it becomes "1". Therefore,
The output signal of the low-pass filter 35 is passed through the flip-flop 3 every (m+1) bits, as shown in b.
When the Q terminal output of 4 is "1", it is at high level H, but becomes "0" after (m+1) bits due to the occurrence of a transmission error, so it becomes low level L.
By comparing the levels of the output signals of the low-pass filter 35, it is possible to detect the occurrence of a transmission error.

[Problem that the invention seeks to solve]

The above-mentioned mB1P code has the advantage that the configuration for error detection is relatively simple, but has the disadvantage that a series of "0"s are likely to occur because it uses even parity.
That is, when the m bits are all "0", the parity bit P is also "0", resulting in a series of "0"s, which has the drawback of making it difficult to reproduce the clock at the relay device or receiving terminal station.

Therefore, the aforementioned mB1C code is used. this
As shown in FIG. 8, the mB1C code adds a check bit C, which is the inversion of the last bit LB of m-bit data, to make (m+1) bits, and m bits are all "0". In the case of ``, check bit C is added as ``1'' because the last bit LB is ``0''. Therefore, the number of consecutive "0"s is less than or equal to (m+1) bits, and if m is 8, the maximum number of consecutive "0"s is 9 when the previous check bit C is "0", and the next Since a check bit C of "1" is added to the clock, clock reproduction on the receiving side is facilitated.

However, error detection in the received data of this mB1C code cannot be detected with the simple configuration shown in FIG. In other words, since it is not determined whether the number of "1"s in (m+1) bits is even or odd,
The Q terminal output of the flip-flop 34 in FIG. 6 changes every (m+1) bits regardless of the presence or absence of a transmission error. Therefore, to detect a transmission error in the mB1C code, the last bit LB and check bit C are compared with each other by synchronizing each (m+1) bit. At the receiving end station,
However, since the relay device is not equipped with a synchronization means, a synchronization circuit must be provided to detect transmission errors, which complicates the configuration of the relay device. However, it had the disadvantage of increasing costs.

The present invention aims to improve these drawbacks.

[Means for solving problems]

In an error detection method in data transmission using mB1C code, the present invention provides a first exclusive logic that calculates the exclusive OR of data of mB1C code and data obtained by delaying this data by 1 bit. sum circuit and
(m+1) bit delay circuit; a second exclusive OR circuit that adds the output signal of the first exclusive OR circuit and the output signal of the delay circuit; An inverting circuit that inverts the output signal of the circuit and applies it to the delay circuit, and a low-pass filter that applies the output signal of the second exclusive logic circuit are provided, and a point of change in the output signal level of the low-pass filter is detected. This is used to detect transmission errors.

[Effect]

The first exclusive OR circuit compares the received data of mB1C codes that are shifted by one bit from each other, and the last bit LB of m bits is compared with the check bit C. Further, the second exclusive OR circuit outputs the output signal of the first exclusive OR circuit and a signal obtained by inverting the output signal of the second exclusive OR circuit and delaying it by (m+1) bits. If the comparison is made and there is no transmission error, then (m+1)
A signal with the same polarity is output for each bit, and if there is a transmission error, a signal with the polarity inverted is output.
Therefore, the output signal of the low-pass filter changes in level due to the occurrence of a transmission error, and transmission errors are detected by identifying the change in the output signal level.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which 1 is an input terminal for mB1C code reception data, 2
is a 1-bit delay circuit, 3 is a first exclusive OR circuit, 4 is a second exclusive OR circuit, 5 is an inverter, 6 is a (m+1) bit delay circuit, 7 is a low-pass filter, and 8 is a It is an output terminal. The received data is applied directly from the input terminal 1 to the exclusive OR circuit 3, and the other is applied to the exclusive OR circuit 3 via the 1-bit delay circuit 2, and the output signal is applied to one of the second exclusive OR circuits 4. The output signal of the exclusive OR circuit 4 is applied to the inverter 5 and the low-pass filter 7, and the output signal of the inverter 5 is applied to the exclusive OR circuit 4 via the (m+1)-bit delay circuit 6. This becomes the other input.

FIG. 2 is an explanatory diagram of the operation of the embodiment of the present invention, where a shows an example of received data. When the last bit LB of m bits is "0", the check bit C is "1", and the last bit LB is "0". When bit LB is "1", check bit C is added as "0", and such (m+1) bits of data are received, and E is the last bit.
This indicates that the LB has caused a transmission error.

Further, b indicates the received data delayed by 1 bit by the delay circuit 2, and the exclusive OR circuit 3 compares the received data shifted by 1 bit with each other. Therefore, (m+1) bits are The last bit LB and check bit C are compared each time. As shown in c, the output signal of this exclusive OR circuit 3 becomes "1" if there is no transmission error at the position of check bit C, and if there is a transmission error in the last bit LB or check bit C. , becomes "0". By detecting this “0”, it is possible to detect the occurrence of a transmission error, but (m
+1) If the bits are not synchronized, it will not be possible to distinguish the comparison output from other data.

Therefore, by using a configuration consisting of the second exclusive OR circuit 4, an inverter 5 as an inverting circuit, an (m+1) bit delay circuit 6, and a low-pass filter 7, the transmission error can cause the first exclusive OR circuit 3 to
This makes it possible to easily detect that the output signal of has become "0". That is, in the exclusive OR circuit 4, the output signal of the first exclusive OR circuit 3 and the output signal of the exclusive OR circuit 4 are inverted by the inverter 5, and (m+1) is output by the delay circuit 6.
A bit-delayed signal is input, and if there is no transmission error, the output signal of the exclusive OR circuit 4 will be, for example, "1" every (m+1) bits.
The output signal of the inverter 5 becomes "0" every (m+1) bits, and the output signal of the delay circuit 6 also becomes "0" every (m+1) bits. However, due to the above-mentioned transmission error indicated by E, the output signal of the first exclusive OR circuit 3 becomes as indicated by c, and the output signal of the first exclusive OR circuit 3 becomes as indicated by c.
The output signal of is shown in d. Therefore, the second
The output signal of the exclusive OR circuit 4 is as shown in e. When there is no transmission error, each (m+1) bit is, for example, "1", but when a transmission error occurs, it is inverted and becomes "1". 0”. If a transmission error occurs again after that, each (m+1) bit is inverted again and becomes "1".

When the output signal of the low-pass filter 7 becomes "1" every (m+1) bits, as shown in f,
Since the probability of occurrence of "1" in m-bit data is 1/2, it becomes a high level H, and when a transmission error occurs and every (m+1) bit becomes "0", it becomes a low level L. . Therefore, by detecting the level inversion between the high level H and the low level L, it is possible to detect that a transmission error has occurred. As such level reversal detection means, various known means can be employed.

FIG. 3 is a block diagram of another embodiment of the present invention, in which the same reference numerals as in FIG. 1 indicate the same parts;
10 is a flip-flop, and CLK is an input terminal for a clock signal. The received data is applied from input terminal 1 to data terminal D of flip-flop 9,
Since the clock signal is applied to the clock terminals C of the flip-flops 9 and 10, data synchronized with the clock signal is output from the Q terminals of the flip-flops 9 and 10, and the data is outputted from the Q terminals of the flip-flops 9 and 10, respectively.
becomes the input. Also, with respect to the Q terminal output of flip-flop 9, the Q terminal output of flip-flop 10 is delayed by one clock signal, that is, one bit. Therefore, the flip-flops 9 and 10 are
It synchronizes received data with a clock signal and constitutes a 1-bit delay circuit.

A second exclusive OR circuit 4 to which the output signal of the exclusive OR circuit 3 is added, an inverter 5, and a delay circuit 6
The operations of the low-pass filter 7 and the low-pass filter 7 are the same as those of the above-mentioned embodiments, and the explanation will be omitted since it will be redundant.

FIG. 4 is a block diagram of still another embodiment of the present invention, in which 11 is a flip-flop, 12 is a 1-bit delay circuit, 13 is a first exclusive OR circuit,
a second exclusive OR circuit having 14 inverted output terminals; 15, 17, and 20 are NAND circuits; 19 is a gate circuit; 16 is a (m+1)-bit delay circuit;
18 is a flip-flop, 21 is a low-pass filter, 22 is an amplifier, 23 is a comparator, 24 is a monostable multivibrator, 25 is a reference voltage input terminal,
26 is an output terminal, 27 is an input terminal for receiving data,
28 is an input terminal for a clock signal.

The received data is applied from input terminal 27 to data terminal D of flip-flop 11, and the clock signal is applied via NAND circuit 20 to clock terminal C of flip-flops 11 and 18. The Q terminal output of flip-flop 11 is directly connected to the first
The terminal output is applied to the exclusive OR circuit 13 via the 1-bit delay circuit 12. Therefore, the received data that is mutually shifted by one bit and inverted is input to the exclusive OR circuit 13, and the comparison result between the last bit LB and check bit C is the same as when there is no transmission error. , becomes "1", and becomes "0" when there is a transmission error. That is, the relationship is opposite to the output signal of the first exclusive OR circuit 3 in FIGS. 1 and 3.

Further, the second exclusive OR circuit 14 applies the output signal from the non-inverting output terminal to the low-pass filter 21, and applies the output signal from the inverting output terminal to the NAND circuit 1.
5 to the delay circuit 16, the output signal is waveform-shaped by the NAND circuit 17, and is applied to the data terminal D of the flip-flop 18, and the Q terminal output is sent to the exclusive OR circuit 1 via the gate circuit 19.
Add to 4. The gate circuit 19 receives the output signal of the first exclusive OR circuit 13 and the flip-flop 1.
This is to match the phase with the Q terminal output signal of No.8.

Even if the output signal of the first exclusive OR circuit 13 is opposite to the embodiment shown in FIGS. 1 and 3, the output signal of the second exclusive OR circuit 14 is the same. Therefore, when a transmission error occurs, (m+1) of the second exclusive OR circuit 14
The output signal for each bit is inverted, the output signal level of the low-pass filter 21 is also inverted, and the amplifier 22 amplifies it, and the comparator 23 inputs a reference voltage corresponding to the midpoint between high level H and low level L. In addition to the terminal 25, when compared, the inversion of the output signal level of the low-pass filter 21 causes the comparator 23 to
The output signal of is also inverted, and when the signal is inverted, the monostable multivibrator 24 is triggered, and a transmission error occurrence detection signal with a predetermined pulse width is output from the output terminal 26.

By counting this detection signal at predetermined time intervals, it is possible to determine the error rate of the transmission path, so that the transmission path can be easily monitored.

In the embodiments described above, the delay circuits 6 and 16 are
Any configuration such as a delay line, shift register, etc. can be adopted as long as the configuration performs a delay of (m+1) bits, and low-pass filters 7 and 21 can be used.
The cutoff frequency is selected depending on the data rate, the value of m, etc. Furthermore, the present invention is not limited to the above-described embodiments, but can be modified in various ways.

〔Effect of the invention〕

As explained above, in a transmission system using mB1C codes, the present invention provides exclusive logic processing of received data and data delayed by 1 bit using first exclusive OR circuits 3 and 13. By calculating the sum, each (m+1) bit becomes "1" (or "0") when there is no transmission error, and "0" when there is a transmission error.
(or "1"), so the output signals of the first exclusive OR circuits 3 and 13 and the output signals of the second exclusive OR circuits 4 and 14 are inverted to (m+1).
The bit-delayed signal is compared by the second exclusive OR circuits 4 and 14, and (m+
1) Since the comparison output signal for each bit is inverted when a transmission error occurs, the occurrence of a transmission error can be easily detected by extracting the DC component using the low-pass filters 7 and 21 and performing level identification. Since no synchronous circuit is required, it can be easily applied to relay devices, and has the advantage of being able to constitute an economical means for monitoring faults in transmission systems.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
The figure is an explanatory diagram of the operation of the embodiment of the present invention, Figures 3 and 4 are block diagrams of different embodiments of the present invention, Figure 5 is an explanatory diagram of the mB1P code, and Figure 6 is the conventional mB1P code. FIG. 7 is an explanatory diagram of the operation of detecting the occurrence of a transmission error, and FIG. 8 is an explanatory diagram of the mB1C code. 1 and 27 are input terminals for received data, 2 and 12 are 1-bit delay circuits, 3 and 13 are first exclusive OR circuits, 4 and 14 are second exclusive OR circuits, and 5
is an inverter, 6 and 16 are (m+1) bit delay circuits, 7 and 21 are low-pass filters, and 8 and 26 are
is an output terminal, 9, 10, 11, and 18 are flip-flops, 22 is an amplifier, 23 is a comparator, and 24 is a monostable multivibrator (MMV).

Claims (1)

[Claims] 1 In an error detection method in data transmission using mB1C code, data of the mB1C code and
a first exclusive OR circuit that performs exclusive OR of the data with data delayed by 1 bit;
1) A delay circuit that delays bits, a second exclusive OR circuit that adds the output signal of the first exclusive OR circuit and the output signal of the delay circuit, and the second exclusive OR circuit. an inverting circuit that inverts the output signal of the second exclusive logic circuit and applies it to the delay circuit, and a low-pass filter that applies the output signal of the second exclusive logic circuit, and detects a level inversion of the output signal of the low-pass filter to detect an error. An error detection method characterized by detecting errors.